forked from OSchip/llvm-project
Merge some tables in generated RegisterInfo file. Store indices into larger table instead of pointers to reduce relocations and shrink table size on 64-bit builds. Shaves ~24K off X86MCTargetDesc.o. Accidentally commited only part of this in r151038.
llvm-svn: 151039
This commit is contained in:
Craig Topper
parent
b5d89e2475
commit
9a511519e4
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@ -255,26 +255,28 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
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const std::string &TargetName = Target.getName();
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OS << "\nnamespace {\n";
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const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
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OS << "extern const unsigned " << TargetName << "RegOverlaps[] = {\n";
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// Emit an overlap list for all registers.
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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const CodeGenRegister *Reg = Regs[i];
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const CodeGenRegister::Set &O = Overlaps[Reg];
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// Move Reg to the front so TRI::getAliasSet can share the list.
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OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { "
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OS << " /* " << Reg->getName() << "_Overlaps */ "
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<< getQualifiedName(Reg->TheDef) << ", ";
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for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
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I != E; ++I)
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if (*I != Reg)
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OS << getQualifiedName((*I)->TheDef) << ", ";
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OS << "0 };\n";
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OS << "0,\n";
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}
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OS << "};\n\n";
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OS << "extern const unsigned " << TargetName << "SubRegsSet[] = {\n";
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// Emit the empty sub-registers list
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OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
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OS << " /* Empty_SubRegsSet */ 0,\n";
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// Loop over all of the registers which have sub-registers, emitting the
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// sub-registers list to memory.
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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@ -284,14 +286,16 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
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// getSubRegs() orders by SubRegIndex. We want a topological order.
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SetVector<CodeGenRegister*> SR;
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Reg.addSubRegsPreOrder(SR, RegBank);
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OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
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OS << " /* " << Reg.getName() << "_SubRegsSet */ ";
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for (unsigned j = 0, je = SR.size(); j != je; ++j)
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OS << getQualifiedName(SR[j]->TheDef) << ", ";
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OS << "0 };\n";
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OS << "0,\n";
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}
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OS << "};\n\n";
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OS << "extern const unsigned " << TargetName << "SuperRegsSet[] = {\n";
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// Emit the empty super-registers list
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OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
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OS << " /* Empty_SuperRegsSet */ 0,\n";
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// Loop over all of the registers which have super-registers, emitting the
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// super-registers list to memory.
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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@ -299,31 +303,42 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
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const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
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if (SR.empty())
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continue;
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OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
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OS << " /* " << Reg.getName() << "_SuperRegsSet */ ";
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for (unsigned j = 0, je = SR.size(); j != je; ++j)
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OS << getQualifiedName(SR[j]->TheDef) << ", ";
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OS << "0 };\n";
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OS << "0,\n";
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}
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OS << "}\n"; // End of anonymous namespace...
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OS << "};\n\n";
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OS << "\nextern const MCRegisterDesc " << TargetName
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OS << "extern const MCRegisterDesc " << TargetName
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<< "RegDesc[] = { // Descriptors\n";
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OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
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OS << " { \"NOREG\", -1, -1, -1 },\n";
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// Now that register alias and sub-registers sets have been emitted, emit the
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// register descriptors now.
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unsigned OverlapsIndex = 0;
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unsigned SubRegIndex = 1; // skip 1 for empty set
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unsigned SuperRegIndex = 1; // skip 1 for empty set
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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const CodeGenRegister &Reg = *Regs[i];
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const CodeGenRegister *Reg = Regs[i];
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OS << " { \"";
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OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
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if (!Reg.getSubRegs().empty())
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OS << Reg.getName() << "_SubRegsSet,\t";
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else
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OS << "Empty_SubRegsSet,\t";
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if (!Reg.getSuperRegs().empty())
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OS << Reg.getName() << "_SuperRegsSet";
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else
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OS << "Empty_SuperRegsSet";
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OS << Reg->getName() << "\", /* " << Reg->getName() << "_Overlaps */ "
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<< OverlapsIndex << ", ";
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OverlapsIndex += Overlaps[Reg].size() + 1;
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if (!Reg->getSubRegs().empty()) {
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OS << "/* " << Reg->getName() << "_SubRegsSet */ " << SubRegIndex
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<< ", ";
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// FIXME not very nice to recalculate this
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SetVector<CodeGenRegister*> SR;
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Reg->addSubRegsPreOrder(SR, RegBank);
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SubRegIndex += SR.size() + 1;
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} else
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OS << "/* Empty_SubRegsSet */ 0, ";
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if (!Reg->getSuperRegs().empty()) {
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OS << "/* " << Reg->getName() << "_SuperRegsSet */ " << SuperRegIndex;
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SuperRegIndex += Reg->getSuperRegs().size() + 1;
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} else
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OS << "/* Empty_SuperRegsSet */ 0";
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OS << " },\n";
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}
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OS << "};\n\n"; // End of register descriptors...
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@ -343,7 +358,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
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// Emit the register list now.
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OS << " // " << Name << " Register Class...\n"
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<< " static const unsigned " << Name
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<< " const unsigned " << Name
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<< "[] = {\n ";
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for (unsigned i = 0, e = Order.size(); i != e; ++i) {
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Record *Reg = Order[i];
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@ -352,7 +367,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
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OS << "\n };\n\n";
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OS << " // " << Name << " Bit set.\n"
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<< " static const unsigned char " << Name
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<< " const unsigned char " << Name
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<< "Bits[] = {\n ";
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BitVectorEmitter BVE;
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for (unsigned i = 0, e = Order.size(); i != e; ++i) {
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@ -390,7 +405,8 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
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<< "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n";
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OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
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<< Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
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<< RegisterClasses.size() << ");\n\n";
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<< RegisterClasses.size() << ", " << TargetName << "RegOverlaps, "
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<< TargetName << "SubRegsSet, " << TargetName << "SuperRegsSet);\n\n";
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EmitRegMapping(OS, Regs, false);
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@ -521,7 +537,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
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// Emit the register list now.
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OS << " // " << Name
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<< " Register Class Value Types...\n"
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<< " static const MVT::SimpleValueType " << Name
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<< " const MVT::SimpleValueType " << Name
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<< "[] = {\n ";
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for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
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OS << getEnumName(RC.VTs[i]) << ", ";
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@ -871,6 +887,9 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
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// Emit the constructor of the class...
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OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
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OS << "extern const unsigned " << TargetName << "RegOverlaps[];\n";
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OS << "extern const unsigned " << TargetName << "SubRegsSet[];\n";
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OS << "extern const unsigned " << TargetName << "SuperRegsSet[];\n";
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OS << ClassName << "::" << ClassName
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<< "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
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@ -879,7 +898,8 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
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<< " " << TargetName << "SubRegIndexTable) {\n"
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<< " InitMCRegisterInfo(" << TargetName << "RegDesc, "
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<< Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
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<< RegisterClasses.size() << ");\n\n";
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<< RegisterClasses.size() << ", " << TargetName << "RegOverlaps, "
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<< TargetName << "SubRegsSet, " << TargetName << "SuperRegsSet);\n\n";
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EmitRegMapping(OS, Regs, true);
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