diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFP.td b/llvm/lib/Target/SystemZ/SystemZInstrFP.td index 16edbea87cda..6318ebc0d68e 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrFP.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrFP.td @@ -65,7 +65,7 @@ let Predicates = [FeatureNoVector] in { // Use a normal load-and-test for compare against zero in case of // vector support (via a pseudo to simplify instruction selection). -let Defs = [CC], usesCustomInserter = 1 in { +let Defs = [CC], usesCustomInserter = 1, hasNoSchedulingInfo = 1 in { def LTEBRCompare_VecPseudo : Pseudo<(outs), (ins FP32:$R1, FP32:$R2), []>; def LTDBRCompare_VecPseudo : Pseudo<(outs), (ins FP64:$R1, FP64:$R2), []>; def LTXBRCompare_VecPseudo : Pseudo<(outs), (ins FP128:$R1, FP128:$R2), []>; diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td index 06da66ad8764..c200479577a2 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td @@ -4685,6 +4685,7 @@ class SelectWrapper [(set (vt cls:$dst), (z_select_ccmask cls:$src1, cls:$src2, imm32zx4:$valid, imm32zx4:$cc))]> { let usesCustomInserter = 1; + let hasNoSchedulingInfo = 1; // Although the instructions used by these nodes do not in themselves // change CC, the insertion requires new blocks, and CC cannot be live // across them. @@ -4695,7 +4696,7 @@ class SelectWrapper // Stores $new to $addr if $cc is true ("" case) or false (Inv case). multiclass CondStores { - let Defs = [CC], Uses = [CC], usesCustomInserter = 1, + let Defs = [CC], Uses = [CC], usesCustomInserter = 1, hasNoSchedulingInfo = 1, mayLoad = 1, mayStore = 1 in { def "" : Pseudo<(outs), (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc), diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td index 5c874dea0874..63e8b70dff85 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td @@ -681,7 +681,7 @@ let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { } // Extend GR64s to GR128s. -let usesCustomInserter = 1 in +let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in def ZEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; //===----------------------------------------------------------------------===// @@ -693,7 +693,7 @@ def : Pat<(i64 (anyext GR32:$src)), (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>; // Extend GR64s to GR128s. -let usesCustomInserter = 1 in +let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in def AEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; //===----------------------------------------------------------------------===// @@ -1934,7 +1934,8 @@ let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in { // Transaction Begin let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in { def TBEGIN : SideEffectBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>; - def TBEGIN_nofloat : SideEffectBinarySILPseudo; + let hasNoSchedulingInfo = 1 in + def TBEGIN_nofloat : SideEffectBinarySILPseudo; def TBEGINC : SideEffectBinarySIL<"tbeginc", 0xE561, int_s390_tbeginc, imm32zx16>; } diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td index 0e42fd944a81..051b1a36ff0a 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td @@ -146,22 +146,6 @@ def : InstRW<[FXa, FXa, FXb, Lat3, GroupAlone], (instregex "TLS_(G|L)DCALL$")>; def : InstRW<[FXb, EndGroup], (instregex "Return$")>; def : InstRW<[FXb], (instregex "CondReturn$")>; -//===----------------------------------------------------------------------===// -// Select instructions -//===----------------------------------------------------------------------===// - -// Select pseudo -def : InstRW<[FXa], (instregex "Select(32|64|32Mux)$")>; - -// CondStore pseudos -def : InstRW<[FXa], (instregex "CondStore16(Inv)?$")>; -def : InstRW<[FXa], (instregex "CondStore16Mux(Inv)?$")>; -def : InstRW<[FXa], (instregex "CondStore32(Inv)?$")>; -def : InstRW<[FXa], (instregex "CondStore32Mux(Inv)?$")>; -def : InstRW<[FXa], (instregex "CondStore64(Inv)?$")>; -def : InstRW<[FXa], (instregex "CondStore8(Inv)?$")>; -def : InstRW<[FXa], (instregex "CondStore8Mux(Inv)?$")>; - //===----------------------------------------------------------------------===// // Move instructions //===----------------------------------------------------------------------===// @@ -665,7 +649,7 @@ def : InstRW<[FXa, FXa, FXb, Lat3, GroupAlone], (instregex "BASSM$")>; // Transaction begin def : InstRW<[LSU, LSU, FXb, FXb, FXb, FXb, FXb, Lat15, GroupAlone], - (instregex "TBEGIN(C|_nofloat)?$")>; + (instregex "TBEGIN(C)?$")>; // Transaction end def : InstRW<[FXb, GroupAlone], (instregex "TEND$")>; @@ -695,10 +679,6 @@ def : InstRW<[FXa, FXa, Lat6, GroupAlone], (instregex "FLOGR$")>; // Population count def : InstRW<[FXa, Lat3], (instregex "POPCNT$")>; -// Extend -def : InstRW<[FXa], (instregex "AEXT128$")>; -def : InstRW<[FXa], (instregex "ZEXT128$")>; - // String instructions def : InstRW<[FXa, LSU, Lat30], (instregex "SRST$")>; def : InstRW<[FXa, Lat30], (instregex "SRSTU$")>; @@ -724,14 +704,6 @@ def : InstRW<[], (instregex "Insn.*")>; // ----------------------------- Floating point ----------------------------- // -//===----------------------------------------------------------------------===// -// FP: Select instructions -//===----------------------------------------------------------------------===// - -def : InstRW<[FXa], (instregex "SelectF(32|64|128)$")>; -def : InstRW<[FXa], (instregex "CondStoreF32(Inv)?$")>; -def : InstRW<[FXa], (instregex "CondStoreF64(Inv)?$")>; - //===----------------------------------------------------------------------===// // FP: Move instructions //===----------------------------------------------------------------------===// @@ -748,11 +720,10 @@ def : InstRW<[FXb, FXb, Lat2, GroupAlone], (instregex "LXR$")>; // Load and Test def : InstRW<[VecXsPm, Lat4], (instregex "LT(D|E)BR$")>; -def : InstRW<[VecXsPm, Lat4], (instregex "LTEBRCompare(_VecPseudo)?$")>; -def : InstRW<[VecXsPm, Lat4], (instregex "LTDBRCompare(_VecPseudo)?$")>; +def : InstRW<[VecXsPm, Lat4], (instregex "LTEBRCompare$")>; +def : InstRW<[VecXsPm, Lat4], (instregex "LTDBRCompare$")>; def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "LTXBR$")>; -def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], - (instregex "LTXBRCompare(_VecPseudo)?$")>; +def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "LTXBRCompare$")>; // Copy sign def : InstRW<[VecXsPm], (instregex "CPSDRd(d|s)$")>; diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td index 8921d2b5400d..4a91c49ef54a 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td @@ -147,22 +147,6 @@ def : InstRW<[FXa, FXa, FXb, Lat3, GroupAlone], (instregex "TLS_(G|L)DCALL$")>; def : InstRW<[FXb, EndGroup], (instregex "Return$")>; def : InstRW<[FXb], (instregex "CondReturn$")>; -//===----------------------------------------------------------------------===// -// Select instructions -//===----------------------------------------------------------------------===// - -// Select pseudo -def : InstRW<[FXa], (instregex "Select(32|64|32Mux)$")>; - -// CondStore pseudos -def : InstRW<[FXa], (instregex "CondStore16(Inv)?$")>; -def : InstRW<[FXa], (instregex "CondStore16Mux(Inv)?$")>; -def : InstRW<[FXa], (instregex "CondStore32(Inv)?$")>; -def : InstRW<[FXa], (instregex "CondStore32Mux(Inv)?$")>; -def : InstRW<[FXa], (instregex "CondStore64(Inv)?$")>; -def : InstRW<[FXa], (instregex "CondStore8(Inv)?$")>; -def : InstRW<[FXa], (instregex "CondStore8Mux(Inv)?$")>; - //===----------------------------------------------------------------------===// // Move instructions //===----------------------------------------------------------------------===// @@ -682,7 +666,7 @@ def : InstRW<[FXa, FXa, FXb, Lat3, GroupAlone], (instregex "BASSM$")>; // Transaction begin def : InstRW<[LSU, LSU, FXb, FXb, FXb, FXb, FXb, Lat15, GroupAlone], - (instregex "TBEGIN(C|_nofloat)?$")>; + (instregex "TBEGIN(C)?$")>; // Transaction end def : InstRW<[FXb, GroupAlone], (instregex "TEND$")>; @@ -712,10 +696,6 @@ def : InstRW<[FXa, FXa, Lat4, GroupAlone], (instregex "FLOGR$")>; // Population count def : InstRW<[FXa, Lat3], (instregex "POPCNT$")>; -// Extend -def : InstRW<[FXa], (instregex "AEXT128$")>; -def : InstRW<[FXa], (instregex "ZEXT128$")>; - // String instructions def : InstRW<[FXa, LSU, Lat30], (instregex "SRST$")>; def : InstRW<[FXa, Lat30], (instregex "SRSTU$")>; @@ -741,14 +721,6 @@ def : InstRW<[], (instregex "Insn.*")>; // ----------------------------- Floating point ----------------------------- // -//===----------------------------------------------------------------------===// -// FP: Select instructions -//===----------------------------------------------------------------------===// - -def : InstRW<[FXa], (instregex "Select(F32|F64|F128|VR128)$")>; -def : InstRW<[FXa], (instregex "CondStoreF32(Inv)?$")>; -def : InstRW<[FXa], (instregex "CondStoreF64(Inv)?$")>; - //===----------------------------------------------------------------------===// // FP: Move instructions //===----------------------------------------------------------------------===// @@ -765,11 +737,10 @@ def : InstRW<[FXb, FXb, Lat2, GroupAlone], (instregex "LXR$")>; // Load and Test def : InstRW<[VecXsPm, Lat4], (instregex "LT(D|E)BR$")>; -def : InstRW<[VecXsPm, Lat4], (instregex "LTEBRCompare(_VecPseudo)?$")>; -def : InstRW<[VecXsPm, Lat4], (instregex "LTDBRCompare(_VecPseudo)?$")>; +def : InstRW<[VecXsPm, Lat4], (instregex "LTEBRCompare$")>; +def : InstRW<[VecXsPm, Lat4], (instregex "LTDBRCompare$")>; def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "LTXBR$")>; -def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], - (instregex "LTXBRCompare(_VecPseudo)?$")>; +def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "LTXBRCompare$")>; // Copy sign def : InstRW<[VecXsPm], (instregex "CPSDRd(d|s)$")>; diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td index 1eb24208a1c2..d998ed9db1ca 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td @@ -130,21 +130,6 @@ def : InstRW<[LSU, FXU, FXU, Lat6, GroupAlone], (instregex "TLS_(G|L)DCALL$")>; def : InstRW<[LSU_lat1, EndGroup], (instregex "Return$")>; def : InstRW<[LSU_lat1, EndGroup], (instregex "CondReturn$")>; -//===----------------------------------------------------------------------===// -// Select instructions -//===----------------------------------------------------------------------===// - -// Select pseudo -def : InstRW<[FXU], (instregex "Select(32|64|32Mux)$")>; - -// CondStore pseudos -def : InstRW<[FXU], (instregex "CondStore16(Inv)?$")>; -def : InstRW<[FXU], (instregex "CondStore16Mux(Inv)?$")>; -def : InstRW<[FXU], (instregex "CondStore32(Inv)?$")>; -def : InstRW<[FXU], (instregex "CondStore64(Inv)?$")>; -def : InstRW<[FXU], (instregex "CondStore8(Inv)?$")>; -def : InstRW<[FXU], (instregex "CondStore8Mux(Inv)?$")>; - //===----------------------------------------------------------------------===// // Move instructions //===----------------------------------------------------------------------===// @@ -636,10 +621,6 @@ def : InstRW<[FXU, FXU, Lat7, GroupAlone], (instregex "FLOGR$")>; // Population count def : InstRW<[FXU, Lat3], (instregex "POPCNT$")>; -// Extend -def : InstRW<[FXU], (instregex "AEXT128$")>; -def : InstRW<[FXU], (instregex "ZEXT128$")>; - // String instructions def : InstRW<[FXU, LSU, Lat30], (instregex "SRST$")>; def : InstRW<[FXU, Lat30], (instregex "SRSTU$")>; @@ -665,14 +646,6 @@ def : InstRW<[], (instregex "Insn.*")>; // ----------------------------- Floating point ----------------------------- // -//===----------------------------------------------------------------------===// -// FP: Select instructions -//===----------------------------------------------------------------------===// - -def : InstRW<[FXU], (instregex "SelectF(32|64|128)$")>; -def : InstRW<[FXU], (instregex "CondStoreF32(Inv)?$")>; -def : InstRW<[FXU], (instregex "CondStoreF64(Inv)?$")>; - //===----------------------------------------------------------------------===// // FP: Move instructions //===----------------------------------------------------------------------===// @@ -689,11 +662,10 @@ def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LXR$")>; // Load and Test def : InstRW<[FPU], (instregex "LT(D|E)BR$")>; -def : InstRW<[FPU], (instregex "LTEBRCompare(_VecPseudo)?$")>; -def : InstRW<[FPU], (instregex "LTDBRCompare(_VecPseudo)?$")>; +def : InstRW<[FPU], (instregex "LTEBRCompare$")>; +def : InstRW<[FPU], (instregex "LTDBRCompare$")>; def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "LTXBR$")>; -def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], - (instregex "LTXBRCompare(_VecPseudo)?$")>; +def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "LTXBRCompare$")>; // Copy sign def : InstRW<[FXU, FXU, Lat5, GroupAlone], (instregex "CPSDRd(d|s)$")>; diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td index d8047a723375..29e4742d4a3c 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td @@ -133,21 +133,6 @@ def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "TLS_(G|L)DCALL$")>; def : InstRW<[LSU_lat1, EndGroup], (instregex "Return$")>; def : InstRW<[LSU_lat1], (instregex "CondReturn$")>; -//===----------------------------------------------------------------------===// -// Select instructions -//===----------------------------------------------------------------------===// - -// Select pseudo -def : InstRW<[FXU], (instregex "Select(32|64|32Mux)$")>; - -// CondStore pseudos -def : InstRW<[FXU], (instregex "CondStore16(Inv)?$")>; -def : InstRW<[FXU], (instregex "CondStore16Mux(Inv)?$")>; -def : InstRW<[FXU], (instregex "CondStore32(Inv)?$")>; -def : InstRW<[FXU], (instregex "CondStore64(Inv)?$")>; -def : InstRW<[FXU], (instregex "CondStore8(Inv)?$")>; -def : InstRW<[FXU], (instregex "CondStore8Mux(Inv)?$")>; - //===----------------------------------------------------------------------===// // Move instructions //===----------------------------------------------------------------------===// @@ -644,7 +629,7 @@ def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "BASSM$")>; // Transaction begin def : InstRW<[LSU, LSU, FXU, FXU, FXU, FXU, FXU, Lat15, GroupAlone], - (instregex "TBEGIN(C|_nofloat)?$")>; + (instregex "TBEGIN(C)?$")>; // Transaction end def : InstRW<[LSU, GroupAlone], (instregex "TEND$")>; @@ -674,10 +659,6 @@ def : InstRW<[FXU, FXU, Lat7, GroupAlone], (instregex "FLOGR$")>; // Population count def : InstRW<[FXU, Lat3], (instregex "POPCNT$")>; -// Extend -def : InstRW<[FXU], (instregex "AEXT128$")>; -def : InstRW<[FXU], (instregex "ZEXT128$")>; - // String instructions def : InstRW<[FXU, LSU, Lat30], (instregex "SRST$")>; def : InstRW<[FXU, Lat30], (instregex "SRSTU$")>; @@ -703,14 +684,6 @@ def : InstRW<[], (instregex "Insn.*")>; // ----------------------------- Floating point ----------------------------- // -//===----------------------------------------------------------------------===// -// FP: Select instructions -//===----------------------------------------------------------------------===// - -def : InstRW<[FXU], (instregex "SelectF(32|64|128)$")>; -def : InstRW<[FXU], (instregex "CondStoreF32(Inv)?$")>; -def : InstRW<[FXU], (instregex "CondStoreF64(Inv)?$")>; - //===----------------------------------------------------------------------===// // FP: Move instructions //===----------------------------------------------------------------------===// @@ -727,11 +700,11 @@ def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LXR$")>; // Load and Test def : InstRW<[FPU], (instregex "LT(D|E)BR$")>; -def : InstRW<[FPU], (instregex "LTEBRCompare(_VecPseudo)?$")>; -def : InstRW<[FPU], (instregex "LTDBRCompare(_VecPseudo)?$")>; +def : InstRW<[FPU], (instregex "LTEBRCompare$")>; +def : InstRW<[FPU], (instregex "LTDBRCompare$")>; def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "LTXBR$")>; def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], - (instregex "LTXBRCompare(_VecPseudo)?$")>; + (instregex "LTXBRCompare$")>; // Copy sign def : InstRW<[FXU, FXU, Lat5, GroupAlone], (instregex "CPSDRd(d|s)$")>;