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[SystemZ] Remove scheduling info from some Pseudo instructions (NFC). 

If the MachineInstr uses a custom inserter and is then erased after
instruction selection, there is no use for mapping it to a sched class.

Review: Ulrich Weigand
llvm-svn: 331040
This commit is contained in:
Jonas Paulsson 2018-04-27 14:09:03 +00:00
parent 2fcee8bd52
commit 9a485985cd
7 changed files with 22 additions and 133 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
llvm/lib/Target/SystemZ/SystemZInstrFP.td
View File

@ -65,7 +65,7 @@ let Predicates = [FeatureNoVector] in {
// Use a normal load-and-test for compare against zero in case of
// vector support (via a pseudo to simplify instruction selection).
let Defs = [CC], usesCustomInserter = 1 in {
let Defs = [CC], usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
def LTEBRCompare_VecPseudo : Pseudo<(outs), (ins FP32:$R1, FP32:$R2), []>;
def LTDBRCompare_VecPseudo : Pseudo<(outs), (ins FP64:$R1, FP64:$R2), []>;
def LTXBRCompare_VecPseudo : Pseudo<(outs), (ins FP128:$R1, FP128:$R2), []>;

3
llvm/lib/Target/SystemZ/SystemZInstrFormats.td
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@ -4685,6 +4685,7 @@ class SelectWrapper<ValueType vt, RegisterOperand cls>
[(set (vt cls:$dst), (z_select_ccmask cls:$src1, cls:$src2,
imm32zx4:$valid, imm32zx4:$cc))]> {
let usesCustomInserter = 1;
let hasNoSchedulingInfo = 1;
// Although the instructions used by these nodes do not in themselves
// change CC, the insertion requires new blocks, and CC cannot be live
// across them.
@ -4695,7 +4696,7 @@ class SelectWrapper<ValueType vt, RegisterOperand cls>
// Stores $new to $addr if $cc is true ("" case) or false (Inv case).
multiclass CondStores<RegisterOperand cls, SDPatternOperator store,
SDPatternOperator load, AddressingMode mode> {
let Defs = [CC], Uses = [CC], usesCustomInserter = 1,
let Defs = [CC], Uses = [CC], usesCustomInserter = 1, hasNoSchedulingInfo = 1,
mayLoad = 1, mayStore = 1 in {
def "" : Pseudo<(outs),
(ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),

7
llvm/lib/Target/SystemZ/SystemZInstrInfo.td
View File

@ -681,7 +681,7 @@ let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in {
}
// Extend GR64s to GR128s.
let usesCustomInserter = 1 in
let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in
def ZEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
//===----------------------------------------------------------------------===//
@ -693,7 +693,7 @@ def : Pat<(i64 (anyext GR32:$src)),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>;
// Extend GR64s to GR128s.
let usesCustomInserter = 1 in
let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in
def AEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
//===----------------------------------------------------------------------===//
@ -1934,7 +1934,8 @@ let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in {
// Transaction Begin
let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in {
def TBEGIN : SideEffectBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>;
def TBEGIN_nofloat : SideEffectBinarySILPseudo<z_tbegin_nofloat, imm32zx16>;
let hasNoSchedulingInfo = 1 in
def TBEGIN_nofloat : SideEffectBinarySILPseudo<z_tbegin_nofloat, imm32zx16>;
def TBEGINC : SideEffectBinarySIL<"tbeginc", 0xE561,
int_s390_tbeginc, imm32zx16>;
}

37
llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
View File

@ -146,22 +146,6 @@ def : InstRW<[FXa, FXa, FXb, Lat3, GroupAlone], (instregex "TLS_(G|L)DCALL$")>;
def : InstRW<[FXb, EndGroup], (instregex "Return$")>;
def : InstRW<[FXb], (instregex "CondReturn$")>;
//===----------------------------------------------------------------------===//
// Select instructions
//===----------------------------------------------------------------------===//
// Select pseudo
def : InstRW<[FXa], (instregex "Select(32|64|32Mux)$")>;
// CondStore pseudos
def : InstRW<[FXa], (instregex "CondStore16(Inv)?$")>;
def : InstRW<[FXa], (instregex "CondStore16Mux(Inv)?$")>;
def : InstRW<[FXa], (instregex "CondStore32(Inv)?$")>;
def : InstRW<[FXa], (instregex "CondStore32Mux(Inv)?$")>;
def : InstRW<[FXa], (instregex "CondStore64(Inv)?$")>;
def : InstRW<[FXa], (instregex "CondStore8(Inv)?$")>;
def : InstRW<[FXa], (instregex "CondStore8Mux(Inv)?$")>;
//===----------------------------------------------------------------------===//
// Move instructions
//===----------------------------------------------------------------------===//
@ -665,7 +649,7 @@ def : InstRW<[FXa, FXa, FXb, Lat3, GroupAlone], (instregex "BASSM$")>;
// Transaction begin
def : InstRW<[LSU, LSU, FXb, FXb, FXb, FXb, FXb, Lat15, GroupAlone],
(instregex "TBEGIN(C|_nofloat)?$")>;
(instregex "TBEGIN(C)?$")>;
// Transaction end
def : InstRW<[FXb, GroupAlone], (instregex "TEND$")>;
@ -695,10 +679,6 @@ def : InstRW<[FXa, FXa, Lat6, GroupAlone], (instregex "FLOGR$")>;
// Population count
def : InstRW<[FXa, Lat3], (instregex "POPCNT$")>;
// Extend
def : InstRW<[FXa], (instregex "AEXT128$")>;
def : InstRW<[FXa], (instregex "ZEXT128$")>;
// String instructions
def : InstRW<[FXa, LSU, Lat30], (instregex "SRST$")>;
def : InstRW<[FXa, Lat30], (instregex "SRSTU$")>;
@ -724,14 +704,6 @@ def : InstRW<[], (instregex "Insn.*")>;
// ----------------------------- Floating point ----------------------------- //
//===----------------------------------------------------------------------===//
// FP: Select instructions
//===----------------------------------------------------------------------===//
def : InstRW<[FXa], (instregex "SelectF(32|64|128)$")>;
def : InstRW<[FXa], (instregex "CondStoreF32(Inv)?$")>;
def : InstRW<[FXa], (instregex "CondStoreF64(Inv)?$")>;
//===----------------------------------------------------------------------===//
// FP: Move instructions
//===----------------------------------------------------------------------===//
@ -748,11 +720,10 @@ def : InstRW<[FXb, FXb, Lat2, GroupAlone], (instregex "LXR$")>;
// Load and Test
def : InstRW<[VecXsPm, Lat4], (instregex "LT(D|E)BR$")>;
def : InstRW<[VecXsPm, Lat4], (instregex "LTEBRCompare(_VecPseudo)?$")>;
def : InstRW<[VecXsPm, Lat4], (instregex "LTDBRCompare(_VecPseudo)?$")>;
def : InstRW<[VecXsPm, Lat4], (instregex "LTEBRCompare$")>;
def : InstRW<[VecXsPm, Lat4], (instregex "LTDBRCompare$")>;
def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "LTXBR$")>;
def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone],
(instregex "LTXBRCompare(_VecPseudo)?$")>;
def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "LTXBRCompare$")>;
// Copy sign
def : InstRW<[VecXsPm], (instregex "CPSDRd(d|s)$")>;

37
llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
View File

@ -147,22 +147,6 @@ def : InstRW<[FXa, FXa, FXb, Lat3, GroupAlone], (instregex "TLS_(G|L)DCALL$")>;
def : InstRW<[FXb, EndGroup], (instregex "Return$")>;
def : InstRW<[FXb], (instregex "CondReturn$")>;
//===----------------------------------------------------------------------===//
// Select instructions
//===----------------------------------------------------------------------===//
// Select pseudo
def : InstRW<[FXa], (instregex "Select(32|64|32Mux)$")>;
// CondStore pseudos
def : InstRW<[FXa], (instregex "CondStore16(Inv)?$")>;
def : InstRW<[FXa], (instregex "CondStore16Mux(Inv)?$")>;
def : InstRW<[FXa], (instregex "CondStore32(Inv)?$")>;
def : InstRW<[FXa], (instregex "CondStore32Mux(Inv)?$")>;
def : InstRW<[FXa], (instregex "CondStore64(Inv)?$")>;
def : InstRW<[FXa], (instregex "CondStore8(Inv)?$")>;
def : InstRW<[FXa], (instregex "CondStore8Mux(Inv)?$")>;
//===----------------------------------------------------------------------===//
// Move instructions
//===----------------------------------------------------------------------===//
@ -682,7 +666,7 @@ def : InstRW<[FXa, FXa, FXb, Lat3, GroupAlone], (instregex "BASSM$")>;
// Transaction begin
def : InstRW<[LSU, LSU, FXb, FXb, FXb, FXb, FXb, Lat15, GroupAlone],
(instregex "TBEGIN(C|_nofloat)?$")>;
(instregex "TBEGIN(C)?$")>;
// Transaction end
def : InstRW<[FXb, GroupAlone], (instregex "TEND$")>;
@ -712,10 +696,6 @@ def : InstRW<[FXa, FXa, Lat4, GroupAlone], (instregex "FLOGR$")>;
// Population count
def : InstRW<[FXa, Lat3], (instregex "POPCNT$")>;
// Extend
def : InstRW<[FXa], (instregex "AEXT128$")>;
def : InstRW<[FXa], (instregex "ZEXT128$")>;
// String instructions
def : InstRW<[FXa, LSU, Lat30], (instregex "SRST$")>;
def : InstRW<[FXa, Lat30], (instregex "SRSTU$")>;
@ -741,14 +721,6 @@ def : InstRW<[], (instregex "Insn.*")>;
// ----------------------------- Floating point ----------------------------- //
//===----------------------------------------------------------------------===//
// FP: Select instructions
//===----------------------------------------------------------------------===//
def : InstRW<[FXa], (instregex "Select(F32|F64|F128|VR128)$")>;
def : InstRW<[FXa], (instregex "CondStoreF32(Inv)?$")>;
def : InstRW<[FXa], (instregex "CondStoreF64(Inv)?$")>;
//===----------------------------------------------------------------------===//
// FP: Move instructions
//===----------------------------------------------------------------------===//
@ -765,11 +737,10 @@ def : InstRW<[FXb, FXb, Lat2, GroupAlone], (instregex "LXR$")>;
// Load and Test
def : InstRW<[VecXsPm, Lat4], (instregex "LT(D|E)BR$")>;
def : InstRW<[VecXsPm, Lat4], (instregex "LTEBRCompare(_VecPseudo)?$")>;
def : InstRW<[VecXsPm, Lat4], (instregex "LTDBRCompare(_VecPseudo)?$")>;
def : InstRW<[VecXsPm, Lat4], (instregex "LTEBRCompare$")>;
def : InstRW<[VecXsPm, Lat4], (instregex "LTDBRCompare$")>;
def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "LTXBR$")>;
def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone],
(instregex "LTXBRCompare(_VecPseudo)?$")>;
def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "LTXBRCompare$")>;
// Copy sign
def : InstRW<[VecXsPm], (instregex "CPSDRd(d|s)$")>;

34
llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
View File

@ -130,21 +130,6 @@ def : InstRW<[LSU, FXU, FXU, Lat6, GroupAlone], (instregex "TLS_(G|L)DCALL$")>;
def : InstRW<[LSU_lat1, EndGroup], (instregex "Return$")>;
def : InstRW<[LSU_lat1, EndGroup], (instregex "CondReturn$")>;
//===----------------------------------------------------------------------===//
// Select instructions
//===----------------------------------------------------------------------===//
// Select pseudo
def : InstRW<[FXU], (instregex "Select(32|64|32Mux)$")>;
// CondStore pseudos
def : InstRW<[FXU], (instregex "CondStore16(Inv)?$")>;
def : InstRW<[FXU], (instregex "CondStore16Mux(Inv)?$")>;
def : InstRW<[FXU], (instregex "CondStore32(Inv)?$")>;
def : InstRW<[FXU], (instregex "CondStore64(Inv)?$")>;
def : InstRW<[FXU], (instregex "CondStore8(Inv)?$")>;
def : InstRW<[FXU], (instregex "CondStore8Mux(Inv)?$")>;
//===----------------------------------------------------------------------===//
// Move instructions
//===----------------------------------------------------------------------===//
@ -636,10 +621,6 @@ def : InstRW<[FXU, FXU, Lat7, GroupAlone], (instregex "FLOGR$")>;
// Population count
def : InstRW<[FXU, Lat3], (instregex "POPCNT$")>;
// Extend
def : InstRW<[FXU], (instregex "AEXT128$")>;
def : InstRW<[FXU], (instregex "ZEXT128$")>;
// String instructions
def : InstRW<[FXU, LSU, Lat30], (instregex "SRST$")>;
def : InstRW<[FXU, Lat30], (instregex "SRSTU$")>;
@ -665,14 +646,6 @@ def : InstRW<[], (instregex "Insn.*")>;
// ----------------------------- Floating point ----------------------------- //
//===----------------------------------------------------------------------===//
// FP: Select instructions
//===----------------------------------------------------------------------===//
def : InstRW<[FXU], (instregex "SelectF(32|64|128)$")>;
def : InstRW<[FXU], (instregex "CondStoreF32(Inv)?$")>;
def : InstRW<[FXU], (instregex "CondStoreF64(Inv)?$")>;
//===----------------------------------------------------------------------===//
// FP: Move instructions
//===----------------------------------------------------------------------===//
@ -689,11 +662,10 @@ def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LXR$")>;
// Load and Test
def : InstRW<[FPU], (instregex "LT(D|E)BR$")>;
def : InstRW<[FPU], (instregex "LTEBRCompare(_VecPseudo)?$")>;
def : InstRW<[FPU], (instregex "LTDBRCompare(_VecPseudo)?$")>;
def : InstRW<[FPU], (instregex "LTEBRCompare$")>;
def : InstRW<[FPU], (instregex "LTDBRCompare$")>;
def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "LTXBR$")>;
def : InstRW<[FPU2, FPU2, Lat9, GroupAlone],
(instregex "LTXBRCompare(_VecPseudo)?$")>;
def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "LTXBRCompare$")>;
// Copy sign
def : InstRW<[FXU, FXU, Lat5, GroupAlone], (instregex "CPSDRd(d|s)$")>;

35
llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
View File

@ -133,21 +133,6 @@ def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "TLS_(G|L)DCALL$")>;
def : InstRW<[LSU_lat1, EndGroup], (instregex "Return$")>;
def : InstRW<[LSU_lat1], (instregex "CondReturn$")>;
//===----------------------------------------------------------------------===//
// Select instructions
//===----------------------------------------------------------------------===//
// Select pseudo
def : InstRW<[FXU], (instregex "Select(32|64|32Mux)$")>;
// CondStore pseudos
def : InstRW<[FXU], (instregex "CondStore16(Inv)?$")>;
def : InstRW<[FXU], (instregex "CondStore16Mux(Inv)?$")>;
def : InstRW<[FXU], (instregex "CondStore32(Inv)?$")>;
def : InstRW<[FXU], (instregex "CondStore64(Inv)?$")>;
def : InstRW<[FXU], (instregex "CondStore8(Inv)?$")>;
def : InstRW<[FXU], (instregex "CondStore8Mux(Inv)?$")>;
//===----------------------------------------------------------------------===//
// Move instructions
//===----------------------------------------------------------------------===//
@ -644,7 +629,7 @@ def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "BASSM$")>;
// Transaction begin
def : InstRW<[LSU, LSU, FXU, FXU, FXU, FXU, FXU, Lat15, GroupAlone],
(instregex "TBEGIN(C|_nofloat)?$")>;
(instregex "TBEGIN(C)?$")>;
// Transaction end
def : InstRW<[LSU, GroupAlone], (instregex "TEND$")>;
@ -674,10 +659,6 @@ def : InstRW<[FXU, FXU, Lat7, GroupAlone], (instregex "FLOGR$")>;
// Population count
def : InstRW<[FXU, Lat3], (instregex "POPCNT$")>;
// Extend
def : InstRW<[FXU], (instregex "AEXT128$")>;
def : InstRW<[FXU], (instregex "ZEXT128$")>;
// String instructions
def : InstRW<[FXU, LSU, Lat30], (instregex "SRST$")>;
def : InstRW<[FXU, Lat30], (instregex "SRSTU$")>;
@ -703,14 +684,6 @@ def : InstRW<[], (instregex "Insn.*")>;
// ----------------------------- Floating point ----------------------------- //
//===----------------------------------------------------------------------===//
// FP: Select instructions
//===----------------------------------------------------------------------===//
def : InstRW<[FXU], (instregex "SelectF(32|64|128)$")>;
def : InstRW<[FXU], (instregex "CondStoreF32(Inv)?$")>;
def : InstRW<[FXU], (instregex "CondStoreF64(Inv)?$")>;
//===----------------------------------------------------------------------===//
// FP: Move instructions
//===----------------------------------------------------------------------===//
@ -727,11 +700,11 @@ def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LXR$")>;
// Load and Test
def : InstRW<[FPU], (instregex "LT(D|E)BR$")>;
def : InstRW<[FPU], (instregex "LTEBRCompare(_VecPseudo)?$")>;
def : InstRW<[FPU], (instregex "LTDBRCompare(_VecPseudo)?$")>;
def : InstRW<[FPU], (instregex "LTEBRCompare$")>;
def : InstRW<[FPU], (instregex "LTDBRCompare$")>;
def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "LTXBR$")>;
def : InstRW<[FPU2, FPU2, Lat9, GroupAlone],
(instregex "LTXBRCompare(_VecPseudo)?$")>;
(instregex "LTXBRCompare$")>;
// Copy sign
def : InstRW<[FXU, FXU, Lat5, GroupAlone], (instregex "CPSDRd(d|s)$")>;