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Add "SkipDead" parameter to TargetInstrInfo::DefinesPredicate 

Some instructions may be removable through processes such as IfConversion,
however DefinesPredicate can not be made aware of when this should be considered.
This parameter allows DefinesPredicate to distinguish these removable instructions
on a per-call basis, allowing for more fine-grained control from processes like
ifConversion.

Renames DefinesPredicate to ClobbersPredicate, to better reflect it's purpose

Differential Revision: https://reviews.llvm.org/D88494
This commit is contained in:
Nicholas Guy 2020-09-28 16:49:41 +01:00
parent bfc961aeb2
commit 9a2d2bedb7
10 changed files with 29 additions and 20 deletions
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9
llvm/include/llvm/CodeGen/TargetInstrInfo.h
View File

@ -1399,8 +1399,13 @@ public:
/// If the specified instruction defines any predicate
/// or condition code register(s) used for predication, returns true as well
/// as the definition predicate(s) by reference.
virtual bool DefinesPredicate(MachineInstr &MI,
std::vector<MachineOperand> &Pred) const {
/// SkipDead should be set to false at any point that dead
/// predicate instructions should be considered as being defined.
/// A dead predicate instruction is one that is guaranteed to be removed
/// after a call to PredicateInstruction.
virtual bool ClobbersPredicate(MachineInstr &MI,
std::vector<MachineOperand> &Pred,
bool SkipDead) const {
return false;
}

4
llvm/lib/CodeGen/IfConversion.cpp
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@ -751,7 +751,7 @@ bool IfConverter::CountDuplicatedInstructions(
// A pred-clobbering instruction in the shared portion prevents
// if-conversion.
std::vector<MachineOperand> PredDefs;
if (TII->DefinesPredicate(*TIB, PredDefs))
if (TII->ClobbersPredicate(*TIB, PredDefs, false))
return false;
// If we get all the way to the branch instructions, don't count them.
if (!TIB->isBranch())
@ -1146,7 +1146,7 @@ void IfConverter::ScanInstructions(BBInfo &BBI,
// FIXME: Make use of PredDefs? e.g. ADDC, SUBC sets predicates but are
// still potentially predicable.
std::vector<MachineOperand> PredDefs;
if (TII->DefinesPredicate(MI, PredDefs))
if (TII->ClobbersPredicate(MI, PredDefs, true))
BBI.ClobbersPred = true;
if (!TII->isPredicable(MI)) {

5
llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
View File

@ -963,8 +963,9 @@ R600InstrInfo::reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) con
return false;
}
bool R600InstrInfo::DefinesPredicate(MachineInstr &MI,
std::vector<MachineOperand> &Pred) const {
bool R600InstrInfo::ClobbersPredicate(MachineInstr &MI,
std::vector<MachineOperand> &Pred,
bool SkipDead) const {
return isPredicateSetter(MI.getOpcode());
}

4
llvm/lib/Target/AMDGPU/R600InstrInfo.h
View File

@ -194,8 +194,8 @@ public:
unsigned NumFCycles, unsigned ExtraFCycles,
BranchProbability Probability) const override;
bool DefinesPredicate(MachineInstr &MI,
std::vector<MachineOperand> &Pred) const override;
bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
bool SkipDead) const override;
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
MachineBasicBlock &FMBB) const override;

5
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -589,8 +589,9 @@ bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
}
}
bool ARMBaseInstrInfo::DefinesPredicate(
MachineInstr &MI, std::vector<MachineOperand> &Pred) const {
bool ARMBaseInstrInfo::ClobbersPredicate(MachineInstr &MI,
std::vector<MachineOperand> &Pred,
bool SkipDead) const {
bool Found = false;
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI.getOperand(i);

4
llvm/lib/Target/ARM/ARMBaseInstrInfo.h
View File

@ -171,8 +171,8 @@ public:
bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
ArrayRef<MachineOperand> Pred2) const override;
bool DefinesPredicate(MachineInstr &MI,
std::vector<MachineOperand> &Pred) const override;
bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
bool SkipDead) const override;
bool isPredicable(const MachineInstr &MI) const override;

5
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -1639,8 +1639,9 @@ bool HexagonInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
return false;
}
bool HexagonInstrInfo::DefinesPredicate(MachineInstr &MI,
std::vector<MachineOperand> &Pred) const {
bool HexagonInstrInfo::ClobbersPredicate(MachineInstr &MI,
std::vector<MachineOperand> &Pred,
bool SkipDead) const {
const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) {

4
llvm/lib/Target/Hexagon/HexagonInstrInfo.h
View File

@ -238,8 +238,8 @@ public:
/// If the specified instruction defines any predicate
/// or condition code register(s) used for predication, returns true as well
/// as the definition predicate(s) by reference.
bool DefinesPredicate(MachineInstr &MI,
std::vector<MachineOperand> &Pred) const override;
bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
bool SkipDead) const override;
/// Return true if the specified instruction can be predicated.
/// By default, this returns true for every instruction with a

5
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -1802,8 +1802,9 @@ bool PPCInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
return false;
}
bool PPCInstrInfo::DefinesPredicate(MachineInstr &MI,
std::vector<MachineOperand> &Pred) const {
bool PPCInstrInfo::ClobbersPredicate(MachineInstr &MI,
std::vector<MachineOperand> &Pred,
bool SkipDead) const {
// Note: At the present time, the contents of Pred from this function is
// unused by IfConversion. This implementation follows ARM by pushing the
// CR-defining operand. Because the 'DZ' and 'DNZ' count as types of

4
llvm/lib/Target/PowerPC/PPCInstrInfo.h
View File

@ -472,8 +472,8 @@ public:
bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
ArrayRef<MachineOperand> Pred2) const override;
bool DefinesPredicate(MachineInstr &MI,
std::vector<MachineOperand> &Pred) const override;
bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
bool SkipDead) const override;
// Comparison optimization.