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rename SDTRet -> SDTNone. 

Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.

llvm-svn: 46017
This commit is contained in:
Chris Lattner 2008-01-15 22:02:54 +00:00
parent 1ba66e0cec
commit 9a249b0ce5
7 changed files with 11 additions and 13 deletions
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2
llvm/lib/Target/ARM/ARMInstrInfo.td
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@ -57,7 +57,7 @@ def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTRet, def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
[SDNPHasChain, SDNPOptInFlag]>; [SDNPHasChain, SDNPOptInFlag]>;
def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,

2
llvm/lib/Target/ARM/ARMInstrVFP.td
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@ -79,7 +79,7 @@ def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>; def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>; def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>; def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTRet, [SDNPInFlag,SDNPOutFlag]>; def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInFlag,SDNPOutFlag]>;
def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>; def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>;
def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutFlag]>; def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutFlag]>;
def arm_fmdrr : SDNode<"ARMISD::FMDRR", SDT_FMDRR>; def arm_fmdrr : SDNode<"ARMISD::FMDRR", SDT_FMDRR>;

2
llvm/lib/Target/Alpha/AlphaInstrInfo.td
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@ -26,7 +26,7 @@ def Alpha_gprello : SDNode<"AlphaISD::GPRelLo", SDTIntBinOp, []>;
def Alpha_gprelhi : SDNode<"AlphaISD::GPRelHi", SDTIntBinOp, []>; def Alpha_gprelhi : SDNode<"AlphaISD::GPRelHi", SDTIntBinOp, []>;
def Alpha_rellit : SDNode<"AlphaISD::RelLit", SDTIntBinOp, [SDNPMayLoad]>; def Alpha_rellit : SDNode<"AlphaISD::RelLit", SDTIntBinOp, [SDNPMayLoad]>;
def retflag : SDNode<"AlphaISD::RET_FLAG", SDTRet, def retflag : SDNode<"AlphaISD::RET_FLAG", SDTNone,
[SDNPHasChain, SDNPOptInFlag]>; [SDNPHasChain, SDNPOptInFlag]>;
// These are target-independent nodes, but have target-specific formats. // These are target-independent nodes, but have target-specific formats.

2
llvm/lib/Target/CellSPU/SPUNodes.td
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@ -222,5 +222,5 @@ class NoEncode<string E> {
// instruction scheduling doesn't disassociate them.) // instruction scheduling doesn't disassociate them.)
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def retflag : SDNode<"SPUISD::RET_FLAG", SDTRet, def retflag : SDNode<"SPUISD::RET_FLAG", SDTNone,
[SDNPHasChain, SDNPOptInFlag]>; [SDNPHasChain, SDNPOptInFlag]>;

6
llvm/lib/Target/PowerPC/PPCInstrInfo.td
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@ -105,13 +105,13 @@ def PPCcall_ELF : SDNode<"PPCISD::CALL_ELF", SDT_PPCCall,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def PPCbctrl_Macho : SDNode<"PPCISD::BCTRL_Macho", SDTRet, def PPCbctrl_Macho : SDNode<"PPCISD::BCTRL_Macho", SDTNone,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def PPCbctrl_ELF : SDNode<"PPCISD::BCTRL_ELF", SDTRet, def PPCbctrl_ELF : SDNode<"PPCISD::BCTRL_ELF", SDTNone,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def retflag : SDNode<"PPCISD::RET_FLAG", SDTRet, def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
[SDNPHasChain, SDNPOptInFlag]>; [SDNPHasChain, SDNPOptInFlag]>;
def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;

6
llvm/lib/Target/TargetSelectionDAG.td
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@ -154,7 +154,7 @@ def SDTBrind : SDTypeProfile<0, 1, [ // brind
SDTCisPtrTy<0> SDTCisPtrTy<0>
]>; ]>;
def SDTRet : SDTypeProfile<0, 0, []>; // ret def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
def SDTLoad : SDTypeProfile<1, 1, [ // load def SDTLoad : SDTypeProfile<1, 1, [ // load
SDTCisPtrTy<1> SDTCisPtrTy<1>
@ -311,7 +311,9 @@ def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
def ret : SDNode<"ISD::RET" , SDTRet, [SDNPHasChain]>; def ret : SDNode<"ISD::RET" , SDTNone, [SDNPHasChain]>;
def trap : SDNode<"ISD::TRAP" , SDTNone,
[SDNPHasChain, SDNPSideEffect]>;
// Do not use ld, st directly. Use load, extload, sextload, zextload, store, // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
// and truncst (see below). // and truncst (see below).

4
llvm/lib/Target/X86/X86InstrInfo.td
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@ -107,10 +107,6 @@ def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
[SDNPHasChain, SDNPOptInFlag]>; [SDNPHasChain, SDNPOptInFlag]>;
def SDT_TRAP : SDTypeProfile<0, 0, []>;
def trap : SDNode<"ISD::TRAP", SDT_TRAP,
[SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// X86 Operand Definitions. // X86 Operand Definitions.
// //