forked from OSchip/llvm-project
[X86] Artificially lower the complexity of the scalar ANDN patterns so that AND with immediate will match first.
This allows the immediate to folded into the and instead of being forced to move into a register. This can sometimes result in shorter encodings since the and can sign extend an immediate. This also allows us to match an and to a movzx after a not. This can cause an extra move if the input to the separate NOT has an additional user which requires a copy before the NOT. llvm-svn: 324260
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@ -1285,12 +1285,13 @@ multiclass bmi_andn<string mnemonic, RegisterClass RC, X86MemOperand x86memop,
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Sched<[WriteALULd, ReadAfterLd]>;
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}
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let Predicates = [HasBMI], Defs = [EFLAGS] in {
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// Complexity is reduced to give and with immediate a chance to match first.
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let Predicates = [HasBMI], Defs = [EFLAGS], AddedComplexity = -6 in {
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defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32>, T8PS, VEX_4V;
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defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64>, T8PS, VEX_4V, VEX_W;
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}
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let Predicates = [HasBMI] in {
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let Predicates = [HasBMI], AddedComplexity = -6 in {
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def : Pat<(and (not GR32:$src1), GR32:$src2),
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(ANDN32rr GR32:$src1, GR32:$src2)>;
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def : Pat<(and (not GR64:$src1), GR64:$src2),
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@ -6687,9 +6687,8 @@ define i32 @mask16_zext(i16 %x) {
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;
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; SKX-LABEL: mask16_zext:
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; SKX: # %bb.0:
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; SKX-NEXT: movl $65535, %eax # imm = 0xFFFF
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; SKX-NEXT: # sched: [1:0.25]
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; SKX-NEXT: andnl %eax, %edi, %eax # sched: [1:0.50]
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; SKX-NEXT: notl %edi # sched: [1:0.25]
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; SKX-NEXT: movzwl %di, %eax # sched: [1:0.25]
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; SKX-NEXT: retq # sched: [7:1.00]
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%m0 = bitcast i16 %x to <16 x i1>
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%m1 = xor <16 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>
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@ -188,8 +188,8 @@ define i1 @and_cmp4(i32 %x, i32 %y) {
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define i1 @and_cmp_const(i32 %x) {
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; CHECK-LABEL: and_cmp_const:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl $43, %eax
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; CHECK-NEXT: andnl %eax, %edi, %eax
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; CHECK-NEXT: notl %edi
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; CHECK-NEXT: andl $43, %edi
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%and = and i32 %x, 43
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@ -12,24 +12,28 @@
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define void @foo() {
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; X86-LABEL: foo:
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; X86: # %bb.0:
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; X86-NEXT: pushl %eax
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; X86-NEXT: pushl %esi
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; X86-NEXT: .cfi_def_cfa_offset 8
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; X86-NEXT: movl d, %eax
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; X86-NEXT: movl d+4, %ecx
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; X86-NEXT: movl $701685459, %edx # imm = 0x29D2DED3
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; X86-NEXT: andnl %edx, %ecx, %ecx
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; X86-NEXT: movl $-564453154, %edx # imm = 0xDE5B20DE
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; X86-NEXT: andnl %edx, %eax, %edx
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; X86-NEXT: shrdl $21, %ecx, %edx
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; X86-NEXT: shrl $21, %ecx
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; X86-NEXT: pushl %eax
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; X86-NEXT: .cfi_def_cfa_offset 12
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; X86-NEXT: .cfi_offset %esi, -8
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; X86-NEXT: movl d, %ecx
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; X86-NEXT: notl %ecx
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; X86-NEXT: movl d+4, %edx
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; X86-NEXT: notl %edx
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; X86-NEXT: andl $701685459, %edx # imm = 0x29D2DED3
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; X86-NEXT: andl $-564453154, %ecx # imm = 0xDE5B20DE
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; X86-NEXT: shrdl $21, %edx, %ecx
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; X86-NEXT: shrl $21, %edx
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; X86-NEXT: xorl %eax, %eax
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; X86-NEXT: testb %al, %al
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; X86-NEXT: cmovnel %ecx, %edx
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; X86-NEXT: cmovnel %eax, %ecx
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; X86-NEXT: movl %edx, %esi
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; X86-NEXT: cmovnel %eax, %esi
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; X86-NEXT: cmovel %ecx, %edx
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; X86-NEXT: andl $-2, %edx
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; X86-NEXT: addl $7, %edx
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; X86-NEXT: adcxl %eax, %ecx
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; X86-NEXT: pushl %ecx
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; X86-NEXT: adcxl %eax, %esi
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; X86-NEXT: pushl %esi
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; X86-NEXT: .cfi_adjust_cfa_offset 4
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; X86-NEXT: pushl %edx
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; X86-NEXT: .cfi_adjust_cfa_offset 4
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@ -37,12 +41,13 @@ define void @foo() {
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; X86-NEXT: .cfi_adjust_cfa_offset 4
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; X86-NEXT: pushl $0
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; X86-NEXT: .cfi_adjust_cfa_offset 4
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; X86-NEXT: calll __divdi3
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; X86-NEXT: calll __divdi3@PLT
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; X86-NEXT: addl $16, %esp
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; X86-NEXT: .cfi_adjust_cfa_offset -16
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; X86-NEXT: orl %eax, %edx
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; X86-NEXT: setne {{[0-9]+}}(%esp)
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; X86-NEXT: popl %eax
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; X86-NEXT: addl $4, %esp
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; X86-NEXT: popl %esi
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; X86-NEXT: retl
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;
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; X64-LABEL: foo:
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