forked from OSchip/llvm-project
[ARM GlobalISel] Support exts and truncs for Thumb2
Mark G_SEXT, G_ZEXT and G_ANYEXT to 32 bits as legal and add support for them in the instruction selector. This uses handwritten code again because the patterns that are generated with TableGen are tuned for what the DAG combiner would produce and not for simple sext/zext nodes. Luckily, we only need to update the opcodes to use the Thumb2 variants, everything else can be reused from ARM. llvm-svn: 349026
This commit is contained in:
Diana Picus
parent
77fc551d1a
commit
99cd644b6c
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@ -229,17 +229,19 @@ static bool selectUnmergeValues(MachineInstrBuilder &MIB,
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/// instruction). Extension operations more complicated than that should not
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/// invoke this. Returns the original opcode if it doesn't know how to select a
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/// better one.
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static unsigned selectSimpleExtOpc(unsigned Opc, unsigned Size) {
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static unsigned selectSimpleExtOpc(unsigned Opc, unsigned Size, bool isThumb) {
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using namespace TargetOpcode;
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if (Size != 8 && Size != 16)
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return Opc;
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if (Opc == G_SEXT)
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return Size == 8 ? ARM::SXTB : ARM::SXTH;
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return isThumb ? Size == 8 ? ARM::t2SXTB : ARM::t2SXTH
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: Size == 8 ? ARM::SXTB : ARM::SXTH;
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if (Opc == G_ZEXT)
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return Size == 8 ? ARM::UXTB : ARM::UXTH;
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return isThumb ? Size == 8 ? ARM::t2UXTB : ARM::t2UXTH
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: Size == 8 ? ARM::UXTB : ARM::UXTH;
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return Opc;
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}
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@ -715,7 +717,7 @@ bool ARMInstructionSelector::select(MachineInstr &I,
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switch (SrcSize) {
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case 1: {
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// ZExt boils down to & 0x1; for SExt we also subtract that from 0
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I.setDesc(TII.get(ARM::ANDri));
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I.setDesc(TII.get(STI.isThumb() ? ARM::t2ANDri : ARM::ANDri));
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MIB.addImm(1).add(predOps(ARMCC::AL)).add(condCodeOp());
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if (isSExt) {
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@ -726,13 +728,13 @@ bool ARMInstructionSelector::select(MachineInstr &I,
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I.getOperand(0).setReg(AndResult);
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auto InsertBefore = std::next(I.getIterator());
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auto SubI =
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BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(ARM::RSBri))
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.addDef(SExtResult)
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.addUse(AndResult)
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.addImm(0)
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.add(predOps(ARMCC::AL))
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.add(condCodeOp());
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auto SubI = BuildMI(MBB, InsertBefore, I.getDebugLoc(),
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TII.get(STI.isThumb() ? ARM::t2RSBri : ARM::RSBri))
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.addDef(SExtResult)
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.addUse(AndResult)
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.addImm(0)
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.add(predOps(ARMCC::AL))
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.add(condCodeOp());
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if (!constrainSelectedInstRegOperands(*SubI, TII, TRI, RBI))
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return false;
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}
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@ -740,7 +742,8 @@ bool ARMInstructionSelector::select(MachineInstr &I,
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}
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case 8:
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case 16: {
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unsigned NewOpc = selectSimpleExtOpc(I.getOpcode(), SrcSize);
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unsigned NewOpc =
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selectSimpleExtOpc(I.getOpcode(), SrcSize, STI.isThumb());
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if (NewOpc == I.getOpcode())
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return false;
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I.setDesc(TII.get(NewOpc));
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@ -82,6 +82,9 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
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return;
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}
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getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
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.legalForCartesianProduct({s32}, {s1, s8, s16});
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// We're keeping these builders around because we'll want to add support for
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// floating point to them.
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auto &LoadStoreBuilder =
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@ -126,9 +129,6 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
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setAction({Op, s32}, Libcall);
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}
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getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
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.legalForCartesianProduct({s32}, {s1, s8, s16});
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getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s32}});
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getActionDefinitionsBuilder(G_PTRTOINT).legalFor({{s32, p0}});
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@ -0,0 +1,79 @@
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# RUN: llc -mtriple arm-- -run-pass=legalizer %s -o - | FileCheck %s
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# RUN: llc -mtriple thumb-- -mattr=+v6t2 -run-pass=legalizer %s -o - | FileCheck %s
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--- |
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define void @test_zext_s16() { ret void }
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define void @test_sext_s8() { ret void }
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define void @test_anyext_s1() { ret void }
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...
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---
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name: test_zext_s16
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# CHECK-LABEL: name: test_zext_s16
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: $r0
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%0(p0) = COPY $r0
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%1(s16) = G_LOAD %0 :: (load 2)
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%2(s32) = G_ZEXT %1
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; G_ZEXT with s16 is legal, so we should find it unchanged in the output
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; CHECK: {{%[0-9]+}}:_(s32) = G_ZEXT {{%[0-9]+}}
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$r0 = COPY %2(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_sext_s8
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# CHECK-LABEL: name: test_sext_s8
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: $r0
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%0(p0) = COPY $r0
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%1(s8) = G_LOAD %0(p0) :: (load 1)
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%2(s32) = G_SEXT %1
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; G_SEXT with s8 is legal, so we should find it unchanged in the output
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; CHECK: {{%[0-9]+}}:_(s32) = G_SEXT {{%[0-9]+}}
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$r0 = COPY %2(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_anyext_s1
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# CHECK-LABEL: name: test_anyext_s1
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: $r0
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%0(p0) = COPY $r0
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%1(s1) = G_LOAD %0(p0) :: (load 1)
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%2(s32) = G_ANYEXT %1
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; G_ANYEXT with s1 is legal, so we should find it unchanged in the output
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; CHECK: {{%[0-9]+}}:_(s32) = G_ANYEXT {{%[0-9]+}}
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$r0 = COPY %2(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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@ -0,0 +1,288 @@
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# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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define void @test_trunc_and_zext_s1() { ret void }
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define void @test_trunc_and_sext_s1() { ret void }
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define void @test_trunc_and_anyext_s1() { ret void }
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define void @test_trunc_and_zext_s8() { ret void }
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define void @test_trunc_and_sext_s8() { ret void }
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define void @test_trunc_and_anyext_s8() { ret void }
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define void @test_trunc_and_zext_s16() { ret void }
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define void @test_trunc_and_sext_s16() { ret void }
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define void @test_trunc_and_anyext_s16() { ret void }
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...
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---
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name: test_trunc_and_zext_s1
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# CHECK-LABEL: name: test_trunc_and_zext_s1
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
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%1(s1) = G_TRUNC %0(s32)
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%2(s32) = G_ZEXT %1(s1)
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; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
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; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREGEXT]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_trunc_and_sext_s1
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# CHECK-LABEL: name: test_trunc_and_sext_s1
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
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%1(s1) = G_TRUNC %0(s32)
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%2(s32) = G_SEXT %1(s1)
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; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
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; CHECK: [[VREGAND:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg
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; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2RSBri [[VREGAND]], 0, 14, $noreg, $noreg
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREGEXT]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_trunc_and_anyext_s1
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# CHECK-LABEL: name: test_trunc_and_anyext_s1
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
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%1(s1) = G_TRUNC %0(s32)
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%2(s32) = G_ANYEXT %1(s1)
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREG]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_trunc_and_zext_s8
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# CHECK-LABEL: name: test_trunc_and_zext_s8
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
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%1(s8) = G_TRUNC %0(s32)
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; CHECK: [[VREGTRUNC:%[0-9]+]]:rgpr = COPY [[VREG]]
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%2(s32) = G_ZEXT %1(s8)
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; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2UXTB [[VREGTRUNC]], 0, 14, $noreg
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREGEXT]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_trunc_and_sext_s8
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# CHECK-LABEL: name: test_trunc_and_sext_s8
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
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%1(s8) = G_TRUNC %0(s32)
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; CHECK: [[VREGTRUNC:%[0-9]+]]:rgpr = COPY [[VREG]]
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%2(s32) = G_SEXT %1(s8)
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; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2SXTB [[VREGTRUNC]], 0, 14, $noreg
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREGEXT]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_trunc_and_anyext_s8
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# CHECK-LABEL: name: test_trunc_and_anyext_s8
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
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%1(s8) = G_TRUNC %0(s32)
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%2(s32) = G_ANYEXT %1(s8)
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREG]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_trunc_and_zext_s16
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# CHECK-LABEL: name: test_trunc_and_zext_s16
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
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%1(s16) = G_TRUNC %0(s32)
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; CHECK: [[VREGTRUNC:%[0-9]+]]:rgpr = COPY [[VREG]]
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%2(s32) = G_ZEXT %1(s16)
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; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2UXTH [[VREGTRUNC]], 0, 14, $noreg
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREGEXT]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_trunc_and_sext_s16
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# CHECK-LABEL: name: test_trunc_and_sext_s16
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
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%1(s16) = G_TRUNC %0(s32)
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; CHECK: [[VREGTRUNC:%[0-9]+]]:rgpr = COPY [[VREG]]
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%2(s32) = G_SEXT %1(s16)
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; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2SXTH [[VREGTRUNC]], 0, 14, $noreg
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREGEXT]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_trunc_and_anyext_s16
|
||||
# CHECK-LABEL: name: test_trunc_and_anyext_s16
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
selected: false
|
||||
# CHECK: selected: true
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gprb }
|
||||
- { id: 1, class: gprb }
|
||||
- { id: 2, class: gprb }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r0
|
||||
|
||||
%0(s32) = COPY $r0
|
||||
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
|
||||
|
||||
%1(s16) = G_TRUNC %0(s32)
|
||||
|
||||
%2(s32) = G_ANYEXT %1(s16)
|
||||
|
||||
$r0 = COPY %2(s32)
|
||||
; CHECK: $r0 = COPY [[VREG]]
|
||||
|
||||
BX_RET 14, $noreg, implicit $r0
|
||||
; CHECK: BX_RET 14, $noreg, implicit $r0
|
||||
...
|
||||
Loading…
Reference in New Issue