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[ARM][SchedModels] Get rid of IsLdrAm2ScaledPred 

Differential revision: https://reviews.llvm.org/D90024
This commit is contained in:
Evgeny Leviant 2020-10-26 12:01:39 +03:00
parent a4fc18e641
commit 99b2756517
4 changed files with 5 additions and 18 deletions
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7
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -634,13 +634,6 @@ bool ARMBaseInstrInfo::isLdstScaledRegNotPlusLsl2(const MachineInstr &MI,
return !SimpleScaled;
}
// Load, scaled register offset
bool ARMBaseInstrInfo::isAm2ScaledReg(const MachineInstr &MI,
unsigned Op) const {
unsigned OffImm = MI.getOperand(Op + 2).getImm();
return ARM_AM::getAM2ShiftOpc(OffImm) != ARM_AM::no_shift;
}
static bool isEligibleForITBlock(const MachineInstr *MI) {
switch (MI->getOpcode()) {
default: return true;

2
llvm/lib/Target/ARM/ARMBaseInstrInfo.h
View File

@ -181,8 +181,6 @@ public:
// Load, scaled register offset, not plus LSL2
bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const;
// Scaled register offset in address mode 2
bool isAm2ScaledReg(const MachineInstr &MI, unsigned Op) const;
/// GetInstSize - Returns the size of the specified MachineInstr.
///

8
llvm/lib/Target/ARM/ARMScheduleA57.td
View File

@ -55,10 +55,6 @@ def IsLdstsoMinusRegPredX0 : MCSchedPredicate<CheckAM2OpSub<2>>;
def IsLdstsoMinusRegPred : MCSchedPredicate<CheckAM2OpSub<3>>;
def IsLdstsoMinusRegPredX2 : MCSchedPredicate<CheckAM2OpSub<4>>;
// Load, scaled register offset
def IsLdrAm2ScaledPred :
SchedPredicate<[{TII->isAm2ScaledReg(*MI, 1)}]>;
// LDM, base reg in list
def IsLDMBaseRegInListPred : MCSchedPredicate<IsLDMBaseRegInList>;
@ -464,11 +460,11 @@ def : InstRW<[A57Write_4cyc_1L_1I, A57WrBackTwo], (instregex "LDR_POST_REG",
"LDRB_POST_REG", "LDR(B?)T_POST$")>;
def A57WriteLdrTRegPost : SchedWriteVariant<[
SchedVar<IsLdrAm2ScaledPred, [A57Write_4cyc_1I_1L_1M]>,
SchedVar<IsLdstsoScaledPredX2, [A57Write_4cyc_1I_1L_1M]>,
SchedVar<NoSchedPred, [A57Write_4cyc_1L_1I]>
]>;
def A57WriteLdrTRegPostWrBack : SchedWriteVariant<[
SchedVar<IsLdrAm2ScaledPred, [A57WrBackThree]>,
SchedVar<IsLdstsoScaledPredX2, [A57WrBackThree]>,
SchedVar<NoSchedPred, [A57WrBackTwo]>
]>;
// 4(3) "I0/I1,L,M" for scaled register, otherwise 4(2) "I0/I1,L"

6
llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
View File

@ -199,7 +199,7 @@
# CHECK-NEXT: 2 4 1.00 * ldrbt r3, [r1], #4
# CHECK-NEXT: 2 4 1.00 * ldrbt r2, [r8], #-8
# CHECK-NEXT: 2 4 1.00 * ldrbt r8, [r7], r6
# CHECK-NEXT: 2 4 1.00 * ldrbt r1, [r2], -r6, lsl #12
# CHECK-NEXT: 3 4 1.00 * ldrbt r1, [r2], -r6, lsl #12
# CHECK-NEXT: 2 4 2.00 * ldrd r0, r1, [r5]
# CHECK-NEXT: 2 4 2.00 * ldrd r0, r1, [r5, r2]
# CHECK-NEXT: 4 5 2.00 * ldrd r0, r1, [r5, -r2]
@ -335,7 +335,7 @@
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6]
# CHECK-NEXT: - 69.00 69.00 167.00 9.00 57.00 - -
# CHECK-NEXT: - 69.00 69.00 167.00 10.00 57.00 - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] Instructions:
@ -371,7 +371,7 @@
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrbt r3, [r1], #4
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrbt r2, [r8], #-8
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrbt r8, [r7], r6
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrbt r1, [r2], -r6, lsl #12
# CHECK-NEXT: - 0.50 0.50 1.00 1.00 - - - ldrbt r1, [r2], -r6, lsl #12
# CHECK-NEXT: - - - 2.00 - - - - ldrd r0, r1, [r5]
# CHECK-NEXT: - - - 2.00 - - - - ldrd r0, r1, [r5, r2]
# CHECK-NEXT: - 1.00 1.00 2.00 - - - - ldrd r0, r1, [r5, -r2]