forked from OSchip/llvm-project
[X86][NFC] Move table from getRelaxedOpcodeArith into its own class
Move out the table and prepare the code to reuse it for the reverse mapping. Follows the example of memory folding/unfolding tables in X86InstrFoldTables.cpp Preparation step to unify `llvm::X86::getRelaxedOpcodeArith` and `getShortArithOpcode` in BOLT X86MCPlusBuilder.cpp. Addresses https://lists.llvm.org/pipermail/llvm-dev/2022-January/154526.html Reviewed By: skan, MaskRay Differential Revision: https://reviews.llvm.org/D121402
This commit is contained in:
Amir Ayupov
parent
ed98c1b376
commit
999fa9f687
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@ -3,6 +3,7 @@ add_llvm_component_library(LLVMX86Desc
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X86IntelInstPrinter.cpp
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X86InstComments.cpp
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X86InstPrinterCommon.cpp
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X86InstrRelaxTables.cpp
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X86ShuffleDecode.cpp
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X86AsmBackend.cpp
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X86MCTargetDesc.cpp
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@ -8,6 +8,7 @@
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#include "MCTargetDesc/X86BaseInfo.h"
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#include "MCTargetDesc/X86FixupKinds.h"
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#include "MCTargetDesc/X86InstrRelaxTables.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/BinaryFormat/ELF.h"
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#include "llvm/BinaryFormat/MachO.h"
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@ -222,87 +223,7 @@ static unsigned getRelaxedOpcodeBranch(const MCInst &Inst, bool Is16BitMode) {
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static unsigned getRelaxedOpcodeArith(const MCInst &Inst) {
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unsigned Op = Inst.getOpcode();
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switch (Op) {
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default:
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return Op;
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// IMUL
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case X86::IMUL16rri8: return X86::IMUL16rri;
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case X86::IMUL16rmi8: return X86::IMUL16rmi;
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case X86::IMUL32rri8: return X86::IMUL32rri;
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case X86::IMUL32rmi8: return X86::IMUL32rmi;
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case X86::IMUL64rri8: return X86::IMUL64rri32;
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case X86::IMUL64rmi8: return X86::IMUL64rmi32;
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// AND
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case X86::AND16ri8: return X86::AND16ri;
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case X86::AND16mi8: return X86::AND16mi;
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case X86::AND32ri8: return X86::AND32ri;
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case X86::AND32mi8: return X86::AND32mi;
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case X86::AND64ri8: return X86::AND64ri32;
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case X86::AND64mi8: return X86::AND64mi32;
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// OR
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case X86::OR16ri8: return X86::OR16ri;
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case X86::OR16mi8: return X86::OR16mi;
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case X86::OR32ri8: return X86::OR32ri;
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case X86::OR32mi8: return X86::OR32mi;
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case X86::OR64ri8: return X86::OR64ri32;
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case X86::OR64mi8: return X86::OR64mi32;
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// XOR
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case X86::XOR16ri8: return X86::XOR16ri;
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case X86::XOR16mi8: return X86::XOR16mi;
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case X86::XOR32ri8: return X86::XOR32ri;
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case X86::XOR32mi8: return X86::XOR32mi;
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case X86::XOR64ri8: return X86::XOR64ri32;
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case X86::XOR64mi8: return X86::XOR64mi32;
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// ADD
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case X86::ADD16ri8: return X86::ADD16ri;
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case X86::ADD16mi8: return X86::ADD16mi;
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case X86::ADD32ri8: return X86::ADD32ri;
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case X86::ADD32mi8: return X86::ADD32mi;
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case X86::ADD64ri8: return X86::ADD64ri32;
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case X86::ADD64mi8: return X86::ADD64mi32;
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// ADC
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case X86::ADC16ri8: return X86::ADC16ri;
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case X86::ADC16mi8: return X86::ADC16mi;
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case X86::ADC32ri8: return X86::ADC32ri;
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case X86::ADC32mi8: return X86::ADC32mi;
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case X86::ADC64ri8: return X86::ADC64ri32;
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case X86::ADC64mi8: return X86::ADC64mi32;
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// SUB
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case X86::SUB16ri8: return X86::SUB16ri;
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case X86::SUB16mi8: return X86::SUB16mi;
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case X86::SUB32ri8: return X86::SUB32ri;
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case X86::SUB32mi8: return X86::SUB32mi;
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case X86::SUB64ri8: return X86::SUB64ri32;
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case X86::SUB64mi8: return X86::SUB64mi32;
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// SBB
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case X86::SBB16ri8: return X86::SBB16ri;
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case X86::SBB16mi8: return X86::SBB16mi;
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case X86::SBB32ri8: return X86::SBB32ri;
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case X86::SBB32mi8: return X86::SBB32mi;
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case X86::SBB64ri8: return X86::SBB64ri32;
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case X86::SBB64mi8: return X86::SBB64mi32;
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// CMP
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case X86::CMP16ri8: return X86::CMP16ri;
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case X86::CMP16mi8: return X86::CMP16mi;
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case X86::CMP32ri8: return X86::CMP32ri;
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case X86::CMP32mi8: return X86::CMP32mi;
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case X86::CMP64ri8: return X86::CMP64ri32;
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case X86::CMP64mi8: return X86::CMP64mi32;
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// PUSH
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case X86::PUSH32i8: return X86::PUSHi32;
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case X86::PUSH16i8: return X86::PUSHi16;
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case X86::PUSH64i8: return X86::PUSH64i32;
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}
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return X86::getRelaxedOpcodeArith(Op);
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}
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static unsigned getRelaxedOpcode(const MCInst &Inst, bool Is16BitMode) {
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@ -0,0 +1,165 @@
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//===- X86InstrRelaxTables.cpp - X86 Instruction Relaxation Tables -*- C++ -*-//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the X86 instruction relaxation tables.
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//
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//===----------------------------------------------------------------------===//
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#include "X86InstrRelaxTables.h"
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#include "X86InstrInfo.h"
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#include "llvm/ADT/STLExtras.h"
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using namespace llvm;
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// These tables are sorted by their ShortOp value allowing them to be binary
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// searched at runtime without the need for additional storage. The enum values
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// are currently emitted in X86GenInstrInfo.inc in alphabetical order. Which
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// makes sorting these tables a simple matter of alphabetizing the table.
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static const X86InstrRelaxTableEntry InstrRelaxTable[] = {
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// ADC
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{ X86::ADC16mi8, X86::ADC16mi },
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{ X86::ADC16ri8, X86::ADC16ri },
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{ X86::ADC32mi8, X86::ADC32mi },
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{ X86::ADC32ri8, X86::ADC32ri },
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{ X86::ADC64mi8, X86::ADC64mi32 },
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{ X86::ADC64ri8, X86::ADC64ri32 },
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// ADD
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{ X86::ADD16mi8, X86::ADD16mi },
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{ X86::ADD16ri8, X86::ADD16ri },
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{ X86::ADD32mi8, X86::ADD32mi },
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{ X86::ADD32ri8, X86::ADD32ri },
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{ X86::ADD64mi8, X86::ADD64mi32 },
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{ X86::ADD64ri8, X86::ADD64ri32 },
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// AND
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{ X86::AND16mi8, X86::AND16mi },
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{ X86::AND16ri8, X86::AND16ri },
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{ X86::AND32mi8, X86::AND32mi },
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{ X86::AND32ri8, X86::AND32ri },
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{ X86::AND64mi8, X86::AND64mi32 },
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{ X86::AND64ri8, X86::AND64ri32 },
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// CMP
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{ X86::CMP16mi8, X86::CMP16mi },
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{ X86::CMP16ri8, X86::CMP16ri },
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{ X86::CMP32mi8, X86::CMP32mi },
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{ X86::CMP32ri8, X86::CMP32ri },
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{ X86::CMP64mi8, X86::CMP64mi32 },
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{ X86::CMP64ri8, X86::CMP64ri32 },
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// IMUL
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{ X86::IMUL16rmi8, X86::IMUL16rmi },
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{ X86::IMUL16rri8, X86::IMUL16rri },
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{ X86::IMUL32rmi8, X86::IMUL32rmi },
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{ X86::IMUL32rri8, X86::IMUL32rri },
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{ X86::IMUL64rmi8, X86::IMUL64rmi32 },
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{ X86::IMUL64rri8, X86::IMUL64rri32 },
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// OR
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{ X86::OR16mi8, X86::OR16mi },
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{ X86::OR16ri8, X86::OR16ri },
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{ X86::OR32mi8, X86::OR32mi },
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{ X86::OR32ri8, X86::OR32ri },
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{ X86::OR64mi8, X86::OR64mi32 },
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{ X86::OR64ri8, X86::OR64ri32 },
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// PUSH
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{ X86::PUSH16i8, X86::PUSHi16 },
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{ X86::PUSH32i8, X86::PUSHi32 },
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{ X86::PUSH64i8, X86::PUSH64i32 },
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// SBB
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{ X86::SBB16mi8, X86::SBB16mi },
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{ X86::SBB16ri8, X86::SBB16ri },
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{ X86::SBB32mi8, X86::SBB32mi },
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{ X86::SBB32ri8, X86::SBB32ri },
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{ X86::SBB64mi8, X86::SBB64mi32 },
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{ X86::SBB64ri8, X86::SBB64ri32 },
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// SUB
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{ X86::SUB16mi8, X86::SUB16mi },
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{ X86::SUB16ri8, X86::SUB16ri },
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{ X86::SUB32mi8, X86::SUB32mi },
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{ X86::SUB32ri8, X86::SUB32ri },
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{ X86::SUB64mi8, X86::SUB64mi32 },
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{ X86::SUB64ri8, X86::SUB64ri32 },
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// XOR
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{ X86::XOR16mi8, X86::XOR16mi },
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{ X86::XOR16ri8, X86::XOR16ri },
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{ X86::XOR32mi8, X86::XOR32mi },
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{ X86::XOR32ri8, X86::XOR32ri },
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{ X86::XOR64mi8, X86::XOR64mi32 },
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{ X86::XOR64ri8, X86::XOR64ri32 },
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};
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static const X86InstrRelaxTableEntry *
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lookupRelaxTableImpl(ArrayRef<X86InstrRelaxTableEntry> Table,
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unsigned ShortOp) {
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#ifndef NDEBUG
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// Make sure the tables are sorted.
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static std::atomic<bool> RelaxTableChecked(false);
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if (!RelaxTableChecked.load(std::memory_order_relaxed)) {
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assert(llvm::is_sorted(InstrRelaxTable) &&
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std::adjacent_find(std::begin(InstrRelaxTable),
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std::end(InstrRelaxTable)) ==
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std::end(InstrRelaxTable) &&
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"InstrRelaxTable is not sorted and unique!");
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RelaxTableChecked.store(true, std::memory_order_relaxed);
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}
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#endif
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const X86InstrRelaxTableEntry *Data = llvm::lower_bound(Table, ShortOp);
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if (Data != Table.end() && Data->KeyOp == ShortOp)
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return Data;
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return nullptr;
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}
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const X86InstrRelaxTableEntry *llvm::lookupRelaxTable(unsigned ShortOp) {
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return lookupRelaxTableImpl(InstrRelaxTable, ShortOp);
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}
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namespace {
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// This class stores the short form tables. It is instantiated as a
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// ManagedStatic to lazily init the short form table.
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struct X86ShortFormTable {
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// Stores relaxation table entries sorted by relaxed form opcode.
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SmallVector<X86InstrRelaxTableEntry, 0> Table;
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X86ShortFormTable() {
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for (const X86InstrRelaxTableEntry &Entry : InstrRelaxTable)
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Table.push_back({Entry.DstOp, Entry.KeyOp});
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llvm::sort(Table);
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// Now that it's sorted, ensure its unique.
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assert(std::adjacent_find(Table.begin(), Table.end()) == Table.end() &&
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"Short form table is not unique!");
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}
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};
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} // namespace
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static ManagedStatic<X86ShortFormTable> ShortTable;
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const X86InstrRelaxTableEntry *llvm::lookupShortTable(unsigned RelaxOp) {
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auto &Table = ShortTable->Table;
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auto I = llvm::lower_bound(Table, RelaxOp);
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if (I != Table.end() && I->KeyOp == RelaxOp)
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return &*I;
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return nullptr;
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}
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namespace llvm {
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/// Get the short instruction opcode for a given relaxed opcode.
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unsigned X86::getShortOpcodeArith(unsigned RelaxOp) {
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if (const X86InstrRelaxTableEntry *I = lookupShortTable(RelaxOp))
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return I->DstOp;
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return RelaxOp;
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}
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/// Get the relaxed instruction opcode for a given short opcode.
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unsigned X86::getRelaxedOpcodeArith(unsigned ShortOp) {
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if (const X86InstrRelaxTableEntry *I = lookupRelaxTable(ShortOp))
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return I->DstOp;
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return ShortOp;
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}
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} // namespace llvm
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@ -0,0 +1,54 @@
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//===-- X86InstrRelaxTables.h - X86 Instruction Relaxation Tables -*- C++ -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the interface to query the X86 instruction relaxation
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// tables.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_X86INSTRRELAXTABLES_H
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#define LLVM_LIB_TARGET_X86_X86INSTRRELAXTABLES_H
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#include <cstdint>
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namespace llvm {
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// This struct is used for both the relaxed and short tables. The KeyOp is used
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// to determine the sorting order.
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struct X86InstrRelaxTableEntry {
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uint16_t KeyOp;
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uint16_t DstOp;
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bool operator<(const X86InstrRelaxTableEntry &RHS) const {
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return KeyOp < RHS.KeyOp;
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}
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bool operator==(const X86InstrRelaxTableEntry &RHS) const {
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return KeyOp == RHS.KeyOp;
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}
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friend bool operator<(const X86InstrRelaxTableEntry &TE, unsigned Opcode) {
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return TE.KeyOp < Opcode;
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}
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};
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/// Look up the relaxed form table entry for a given \p ShortOp.
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const X86InstrRelaxTableEntry *lookupRelaxTable(unsigned ShortOp);
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/// Look up the short form table entry for a given \p RelaxOp.
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const X86InstrRelaxTableEntry *lookupShortTable(unsigned RelaxOp);
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namespace X86 {
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/// Get the short instruction opcode for a given relaxed opcode.
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unsigned getShortOpcodeArith(unsigned RelaxOp);
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/// Get the relaxed instruction opcode for a given short opcode.
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unsigned getRelaxedOpcodeArith(unsigned ShortOp);
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} // namespace X86
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} // namespace llvm
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#endif
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