forked from OSchip/llvm-project
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change. No functionality change intended. llvm-svn: 183572
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@ -41,7 +41,7 @@ using namespace llvm;
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XCoreInstrInfo::XCoreInstrInfo()
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: XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
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RI(*this) {
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RI() {
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}
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static bool isZeroImm(const MachineOperand &op) {
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@ -37,8 +37,8 @@
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using namespace llvm;
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XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
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: XCoreGenRegisterInfo(XCore::LR), TII(tii) {
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XCoreRegisterInfo::XCoreRegisterInfo()
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: XCoreGenRegisterInfo(XCore::LR) {
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}
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// helper functions
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@ -112,6 +112,7 @@ XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int FrameIndex = FrameOp.getIndex();
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MachineFunction &MF = *MI.getParent()->getParent();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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int StackSize = MF.getFrameInfo()->getStackSize();
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@ -249,6 +250,7 @@ loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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report_fatal_error("loadConstant value too big " + Twine(Value));
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}
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int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
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const TargetInstrInfo &TII = *MBB.getParent()->getTarget().getInstrInfo();
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BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
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}
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@ -25,8 +25,6 @@ class TargetInstrInfo;
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struct XCoreRegisterInfo : public XCoreGenRegisterInfo {
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private:
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const TargetInstrInfo &TII;
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void loadConstant(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DstReg, int64_t Value, DebugLoc dl) const;
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@ -40,7 +38,7 @@ private:
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unsigned DstReg, int Offset, DebugLoc dl) const;
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public:
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XCoreRegisterInfo(const TargetInstrInfo &tii);
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XCoreRegisterInfo();
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/// Code Generation virtual methods...
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