forked from OSchip/llvm-project
Add support for the isLoad and isStore flags, needed by the instruction scheduler
llvm-svn: 16554
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9b0dfa3c0d
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@ -71,6 +71,8 @@ namespace llvm {
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bool isBranch;
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bool isBarrier;
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bool isCall;
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bool isLoad;
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bool isStore;
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bool isTwoAddress;
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bool isTerminator;
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bool hasDelaySlot;
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@ -195,6 +195,8 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
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isBranch = R->getValueAsBit("isBranch");
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isBarrier = R->getValueAsBit("isBarrier");
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isCall = R->getValueAsBit("isCall");
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isLoad = R->getValueAsBit("isLoad");
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isStore = R->getValueAsBit("isStore");
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isTwoAddress = R->getValueAsBit("isTwoAddress");
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isTerminator = R->getValueAsBit("isTerminator");
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hasDelaySlot = R->getValueAsBit("hasDelaySlot");
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@ -113,6 +113,8 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
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if (Inst.isBarrier) OS << "|M_BARRIER_FLAG";
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if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
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if (Inst.isCall) OS << "|M_CALL_FLAG";
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if (Inst.isLoad) OS << "|M_LOAD_FLAG";
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if (Inst.isStore) OS << "|M_STORE_FLAG";
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if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG";
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if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
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OS << ", 0";
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