forked from OSchip/llvm-project
[TargetLowering] Simplify the interface for expandCTPOP/expandCTLZ/expandCTTZ.
There is no need to return a bool and have an SDValue output parameter. Just return the SDValue and let the caller check if it is null. I have another patch to add more callers of these so I thought I'd clean up the interface first. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D112267
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@ -4446,23 +4446,20 @@ public:
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/// Expand CTPOP nodes. Expands vector/scalar CTPOP nodes,
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/// vector nodes can only succeed if all operations are legal/custom.
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/// \param N Node to expand
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/// \param Result output after conversion
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/// \returns True, if the expansion was successful, false otherwise
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bool expandCTPOP(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
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/// \returns The expansion result or SDValue() if it fails.
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SDValue expandCTPOP(SDNode *N, SelectionDAG &DAG) const;
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/// Expand CTLZ/CTLZ_ZERO_UNDEF nodes. Expands vector/scalar CTLZ nodes,
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/// vector nodes can only succeed if all operations are legal/custom.
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/// \param N Node to expand
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/// \param Result output after conversion
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/// \returns True, if the expansion was successful, false otherwise
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bool expandCTLZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
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/// \returns The expansion result or SDValue() if it fails.
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SDValue expandCTLZ(SDNode *N, SelectionDAG &DAG) const;
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/// Expand CTTZ/CTTZ_ZERO_UNDEF nodes. Expands vector/scalar CTTZ nodes,
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/// vector nodes can only succeed if all operations are legal/custom.
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/// \param N Node to expand
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/// \param Result output after conversion
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/// \returns True, if the expansion was successful, false otherwise
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bool expandCTTZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
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/// \returns The expansion result or SDValue() if it fails.
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SDValue expandCTTZ(SDNode *N, SelectionDAG &DAG) const;
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/// Expand ABS nodes. Expands vector/scalar ABS nodes,
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/// vector nodes can only succeed if all operations are legal/custom.
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@ -2688,17 +2688,17 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
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Results.push_back(Tmp1);
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break;
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case ISD::CTPOP:
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if (TLI.expandCTPOP(Node, Tmp1, DAG))
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if ((Tmp1 = TLI.expandCTPOP(Node, DAG)))
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Results.push_back(Tmp1);
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break;
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case ISD::CTLZ:
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case ISD::CTLZ_ZERO_UNDEF:
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if (TLI.expandCTLZ(Node, Tmp1, DAG))
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if ((Tmp1 = TLI.expandCTLZ(Node, DAG)))
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Results.push_back(Tmp1);
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break;
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case ISD::CTTZ:
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case ISD::CTTZ_ZERO_UNDEF:
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if (TLI.expandCTTZ(Node, Tmp1, DAG))
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if ((Tmp1 = TLI.expandCTTZ(Node, DAG)))
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Results.push_back(Tmp1);
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break;
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case ISD::BITREVERSE:
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@ -783,22 +783,22 @@ void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
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ExpandBITREVERSE(Node, Results);
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return;
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case ISD::CTPOP:
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if (TLI.expandCTPOP(Node, Tmp, DAG)) {
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Results.push_back(Tmp);
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if (SDValue Expanded = TLI.expandCTPOP(Node, DAG)) {
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Results.push_back(Expanded);
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return;
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}
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break;
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case ISD::CTLZ:
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case ISD::CTLZ_ZERO_UNDEF:
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if (TLI.expandCTLZ(Node, Tmp, DAG)) {
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Results.push_back(Tmp);
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if (SDValue Expanded = TLI.expandCTLZ(Node, DAG)) {
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Results.push_back(Expanded);
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return;
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}
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break;
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case ISD::CTTZ:
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case ISD::CTTZ_ZERO_UNDEF:
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if (TLI.expandCTTZ(Node, Tmp, DAG)) {
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Results.push_back(Tmp);
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if (SDValue Expanded = TLI.expandCTTZ(Node, DAG)) {
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Results.push_back(Expanded);
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return;
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}
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break;
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@ -6991,8 +6991,7 @@ static bool canExpandVectorCTPOP(const TargetLowering &TLI, EVT VT) {
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TLI.isOperationLegalOrCustomOrPromote(ISD::AND, VT);
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}
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bool TargetLowering::expandCTPOP(SDNode *Node, SDValue &Result,
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SelectionDAG &DAG) const {
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SDValue TargetLowering::expandCTPOP(SDNode *Node, SelectionDAG &DAG) const {
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SDLoc dl(Node);
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EVT VT = Node->getValueType(0);
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EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
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@ -7002,11 +7001,11 @@ bool TargetLowering::expandCTPOP(SDNode *Node, SDValue &Result,
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// TODO: Add support for irregular type lengths.
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if (!(Len <= 128 && Len % 8 == 0))
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return false;
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return SDValue();
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// Only expand vector types if we have the appropriate vector bit operations.
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if (VT.isVector() && !canExpandVectorCTPOP(*this, VT))
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return false;
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return SDValue();
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// This is the "best" algorithm from
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// http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
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@ -7043,12 +7042,10 @@ bool TargetLowering::expandCTPOP(SDNode *Node, SDValue &Result,
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DAG.getNode(ISD::SRL, dl, VT, DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
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DAG.getConstant(Len - 8, dl, ShVT));
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Result = Op;
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return true;
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return Op;
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}
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bool TargetLowering::expandCTLZ(SDNode *Node, SDValue &Result,
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SelectionDAG &DAG) const {
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SDValue TargetLowering::expandCTLZ(SDNode *Node, SelectionDAG &DAG) const {
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SDLoc dl(Node);
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EVT VT = Node->getValueType(0);
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EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
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@ -7057,10 +7054,8 @@ bool TargetLowering::expandCTLZ(SDNode *Node, SDValue &Result,
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// If the non-ZERO_UNDEF version is supported we can use that instead.
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if (Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF &&
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isOperationLegalOrCustom(ISD::CTLZ, VT)) {
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Result = DAG.getNode(ISD::CTLZ, dl, VT, Op);
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return true;
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}
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isOperationLegalOrCustom(ISD::CTLZ, VT))
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return DAG.getNode(ISD::CTLZ, dl, VT, Op);
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// If the ZERO_UNDEF version is supported use that and handle the zero case.
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if (isOperationLegalOrCustom(ISD::CTLZ_ZERO_UNDEF, VT)) {
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@ -7069,9 +7064,8 @@ bool TargetLowering::expandCTLZ(SDNode *Node, SDValue &Result,
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SDValue CTLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, VT, Op);
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SDValue Zero = DAG.getConstant(0, dl, VT);
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SDValue SrcIsZero = DAG.getSetCC(dl, SetCCVT, Op, Zero, ISD::SETEQ);
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Result = DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero,
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DAG.getConstant(NumBitsPerElt, dl, VT), CTLZ);
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return true;
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return DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero,
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DAG.getConstant(NumBitsPerElt, dl, VT), CTLZ);
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}
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// Only expand vector types if we have the appropriate vector bit operations.
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@ -7081,7 +7075,7 @@ bool TargetLowering::expandCTLZ(SDNode *Node, SDValue &Result,
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!canExpandVectorCTPOP(*this, VT)) ||
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!isOperationLegalOrCustom(ISD::SRL, VT) ||
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!isOperationLegalOrCustomOrPromote(ISD::OR, VT)))
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return false;
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return SDValue();
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// for now, we do this:
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// x = x | (x >> 1);
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@ -7098,12 +7092,10 @@ bool TargetLowering::expandCTLZ(SDNode *Node, SDValue &Result,
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DAG.getNode(ISD::SRL, dl, VT, Op, Tmp));
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}
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Op = DAG.getNOT(dl, Op, VT);
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Result = DAG.getNode(ISD::CTPOP, dl, VT, Op);
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return true;
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return DAG.getNode(ISD::CTPOP, dl, VT, Op);
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}
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bool TargetLowering::expandCTTZ(SDNode *Node, SDValue &Result,
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SelectionDAG &DAG) const {
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SDValue TargetLowering::expandCTTZ(SDNode *Node, SelectionDAG &DAG) const {
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SDLoc dl(Node);
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EVT VT = Node->getValueType(0);
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SDValue Op = Node->getOperand(0);
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@ -7111,10 +7103,8 @@ bool TargetLowering::expandCTTZ(SDNode *Node, SDValue &Result,
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// If the non-ZERO_UNDEF version is supported we can use that instead.
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if (Node->getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
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isOperationLegalOrCustom(ISD::CTTZ, VT)) {
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Result = DAG.getNode(ISD::CTTZ, dl, VT, Op);
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return true;
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}
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isOperationLegalOrCustom(ISD::CTTZ, VT))
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return DAG.getNode(ISD::CTTZ, dl, VT, Op);
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// If the ZERO_UNDEF version is supported use that and handle the zero case.
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if (isOperationLegalOrCustom(ISD::CTTZ_ZERO_UNDEF, VT)) {
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@ -7123,9 +7113,8 @@ bool TargetLowering::expandCTTZ(SDNode *Node, SDValue &Result,
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SDValue CTTZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, VT, Op);
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SDValue Zero = DAG.getConstant(0, dl, VT);
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SDValue SrcIsZero = DAG.getSetCC(dl, SetCCVT, Op, Zero, ISD::SETEQ);
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Result = DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero,
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DAG.getConstant(NumBitsPerElt, dl, VT), CTTZ);
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return true;
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return DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero,
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DAG.getConstant(NumBitsPerElt, dl, VT), CTTZ);
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}
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// Only expand vector types if we have the appropriate vector bit operations.
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@ -7137,7 +7126,7 @@ bool TargetLowering::expandCTTZ(SDNode *Node, SDValue &Result,
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!isOperationLegalOrCustom(ISD::SUB, VT) ||
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!isOperationLegalOrCustomOrPromote(ISD::AND, VT) ||
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!isOperationLegalOrCustomOrPromote(ISD::XOR, VT)))
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return false;
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return SDValue();
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// for now, we use: { return popcount(~x & (x - 1)); }
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// unless the target has ctlz but not ctpop, in which case we use:
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@ -7149,14 +7138,11 @@ bool TargetLowering::expandCTTZ(SDNode *Node, SDValue &Result,
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// If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
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if (isOperationLegal(ISD::CTLZ, VT) && !isOperationLegal(ISD::CTPOP, VT)) {
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Result =
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DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(NumBitsPerElt, dl, VT),
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DAG.getNode(ISD::CTLZ, dl, VT, Tmp));
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return true;
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return DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(NumBitsPerElt, dl, VT),
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DAG.getNode(ISD::CTLZ, dl, VT, Tmp));
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}
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Result = DAG.getNode(ISD::CTPOP, dl, VT, Tmp);
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return true;
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return DAG.getNode(ISD::CTPOP, dl, VT, Tmp);
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}
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bool TargetLowering::expandABS(SDNode *N, SDValue &Result,
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