forked from OSchip/llvm-project
AMDGPU: Fix promoting f16 fpowi with legal f16
This commit is contained in:
Matt Arsenault
parent
63f0b10b8c
commit
994fb86bc2
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@ -449,6 +449,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
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if (Subtarget->has16BitInsts()) {
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setOperationAction(ISD::FPOW, MVT::f16, Promote);
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setOperationAction(ISD::FPOWI, MVT::f16, Promote);
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setOperationAction(ISD::FLOG, MVT::f16, Custom);
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setOperationAction(ISD::FEXP, MVT::f16, Custom);
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setOperationAction(ISD::FLOG10, MVT::f16, Custom);
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@ -0,0 +1,250 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii < %s | FileCheck -check-prefixes=GCN,GFX7 %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s
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define i16 @v_powi_f16(i16 %l, i32 %r) {
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; GCN-LABEL: v_powi_f16:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0
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; GCN-NEXT: v_cvt_f32_i32_e32 v1, v1
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; GCN-NEXT: v_log_f32_e32 v0, v0
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; GCN-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
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; GCN-NEXT: v_exp_f32_e32 v0, v0
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; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%l.cast = bitcast i16 %l to half
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%res = call half @llvm.powi.f16(half %l.cast, i32 %r)
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%res.cast = bitcast half %res to i16
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ret i16 %res.cast
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}
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define float @v_powi_f32(float %l, i32 %r) {
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; GCN-LABEL: v_powi_f32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_log_f32_e32 v0, v0
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; GCN-NEXT: v_cvt_f32_i32_e32 v1, v1
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; GCN-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
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; GCN-NEXT: v_exp_f32_e32 v0, v0
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%res = call float @llvm.powi.f32(float %l, i32 %r)
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ret float %res
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}
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define float @v_powi_0_f32(float %l) {
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; GCN-LABEL: v_powi_0_f32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v0, 1.0
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%res = call float @llvm.powi.f32(float %l, i32 0)
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ret float %res
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}
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define float @v_powi_1_f32(float %l) {
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; GCN-LABEL: v_powi_1_f32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%res = call float @llvm.powi.f32(float %l, i32 1)
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ret float %res
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}
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define float @v_powi_neg1_f32(float %l) {
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; GFX7-LABEL: v_powi_neg1_f32:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
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; GFX7-NEXT: v_rcp_f32_e32 v2, v1
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; GFX7-NEXT: v_fma_f32 v3, -v1, v2, 1.0
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; GFX7-NEXT: v_fma_f32 v2, v3, v2, v2
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; GFX7-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
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; GFX7-NEXT: v_mul_f32_e32 v4, v3, v2
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; GFX7-NEXT: v_fma_f32 v5, -v1, v4, v3
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; GFX7-NEXT: v_fma_f32 v4, v5, v2, v4
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; GFX7-NEXT: v_fma_f32 v1, -v1, v4, v3
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; GFX7-NEXT: v_div_fmas_f32 v1, v1, v2, v4
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; GFX7-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
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; GFX7-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX8-LABEL: v_powi_neg1_f32:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
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; GFX8-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
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; GFX8-NEXT: v_rcp_f32_e32 v3, v1
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; GFX8-NEXT: v_fma_f32 v4, -v1, v3, 1.0
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; GFX8-NEXT: v_fma_f32 v3, v4, v3, v3
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; GFX8-NEXT: v_mul_f32_e32 v4, v2, v3
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; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v2
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; GFX8-NEXT: v_fma_f32 v4, v5, v3, v4
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; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v2
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; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4
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; GFX8-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
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; GFX8-NEXT: s_setpc_b64 s[30:31]
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%res = call float @llvm.powi.f32(float %l, i32 -1)
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ret float %res
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}
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define float @v_powi_2_f32(float %l) {
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; GCN-LABEL: v_powi_2_f32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_mul_f32_e32 v0, v0, v0
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%res = call float @llvm.powi.f32(float %l, i32 2)
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ret float %res
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}
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define float @v_powi_neg2_f32(float %l) {
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; GFX7-LABEL: v_powi_neg2_f32:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7-NEXT: v_mul_f32_e32 v0, v0, v0
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; GFX7-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
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; GFX7-NEXT: v_rcp_f32_e32 v2, v1
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; GFX7-NEXT: v_fma_f32 v3, -v1, v2, 1.0
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; GFX7-NEXT: v_fma_f32 v2, v3, v2, v2
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; GFX7-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
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; GFX7-NEXT: v_mul_f32_e32 v4, v3, v2
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; GFX7-NEXT: v_fma_f32 v5, -v1, v4, v3
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; GFX7-NEXT: v_fma_f32 v4, v5, v2, v4
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; GFX7-NEXT: v_fma_f32 v1, -v1, v4, v3
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; GFX7-NEXT: v_div_fmas_f32 v1, v1, v2, v4
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; GFX7-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
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; GFX7-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX8-LABEL: v_powi_neg2_f32:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-NEXT: v_mul_f32_e32 v0, v0, v0
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; GFX8-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
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; GFX8-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
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; GFX8-NEXT: v_rcp_f32_e32 v3, v1
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; GFX8-NEXT: v_fma_f32 v4, -v1, v3, 1.0
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; GFX8-NEXT: v_fma_f32 v3, v4, v3, v3
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; GFX8-NEXT: v_mul_f32_e32 v4, v2, v3
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; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v2
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; GFX8-NEXT: v_fma_f32 v4, v5, v3, v4
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; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v2
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; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4
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; GFX8-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
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; GFX8-NEXT: s_setpc_b64 s[30:31]
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%res = call float @llvm.powi.f32(float %l, i32 -2)
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ret float %res
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}
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define float @v_powi_4_f32(float %l) {
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; GCN-LABEL: v_powi_4_f32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_mul_f32_e32 v0, v0, v0
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; GCN-NEXT: v_mul_f32_e32 v0, v0, v0
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%res = call float @llvm.powi.f32(float %l, i32 4)
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ret float %res
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}
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define float @v_powi_8_f32(float %l) {
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; GCN-LABEL: v_powi_8_f32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_mul_f32_e32 v0, v0, v0
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; GCN-NEXT: v_mul_f32_e32 v0, v0, v0
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; GCN-NEXT: v_mul_f32_e32 v0, v0, v0
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%res = call float @llvm.powi.f32(float %l, i32 8)
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ret float %res
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}
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define float @v_powi_16_f32(float %l) {
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; GCN-LABEL: v_powi_16_f32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_mul_f32_e32 v0, v0, v0
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; GCN-NEXT: v_mul_f32_e32 v0, v0, v0
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; GCN-NEXT: v_mul_f32_e32 v0, v0, v0
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; GCN-NEXT: v_mul_f32_e32 v0, v0, v0
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%res = call float @llvm.powi.f32(float %l, i32 16)
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ret float %res
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}
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define float @v_powi_128_f32(float %l) {
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; GCN-LABEL: v_powi_128_f32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_mul_f32_e32 v0, v0, v0
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; GCN-NEXT: v_mul_f32_e32 v0, v0, v0
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; GCN-NEXT: v_mul_f32_e32 v0, v0, v0
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; GCN-NEXT: v_mul_f32_e32 v0, v0, v0
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; GCN-NEXT: v_mul_f32_e32 v0, v0, v0
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; GCN-NEXT: v_mul_f32_e32 v0, v0, v0
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; GCN-NEXT: v_mul_f32_e32 v0, v0, v0
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%res = call float @llvm.powi.f32(float %l, i32 128)
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ret float %res
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}
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define float @v_powi_neg128_f32(float %l) {
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; GFX7-LABEL: v_powi_neg128_f32:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7-NEXT: v_mul_f32_e32 v0, v0, v0
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; GFX7-NEXT: v_mul_f32_e32 v0, v0, v0
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; GFX7-NEXT: v_mul_f32_e32 v0, v0, v0
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; GFX7-NEXT: v_mul_f32_e32 v0, v0, v0
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; GFX7-NEXT: v_mul_f32_e32 v0, v0, v0
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; GFX7-NEXT: v_mul_f32_e32 v0, v0, v0
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; GFX7-NEXT: v_mul_f32_e32 v0, v0, v0
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; GFX7-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
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; GFX7-NEXT: v_rcp_f32_e32 v2, v1
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; GFX7-NEXT: v_fma_f32 v3, -v1, v2, 1.0
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; GFX7-NEXT: v_fma_f32 v2, v3, v2, v2
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; GFX7-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
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; GFX7-NEXT: v_mul_f32_e32 v4, v3, v2
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; GFX7-NEXT: v_fma_f32 v5, -v1, v4, v3
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; GFX7-NEXT: v_fma_f32 v4, v5, v2, v4
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; GFX7-NEXT: v_fma_f32 v1, -v1, v4, v3
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; GFX7-NEXT: v_div_fmas_f32 v1, v1, v2, v4
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; GFX7-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
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; GFX7-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX8-LABEL: v_powi_neg128_f32:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-NEXT: v_mul_f32_e32 v0, v0, v0
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; GFX8-NEXT: v_mul_f32_e32 v0, v0, v0
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; GFX8-NEXT: v_mul_f32_e32 v0, v0, v0
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; GFX8-NEXT: v_mul_f32_e32 v0, v0, v0
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; GFX8-NEXT: v_mul_f32_e32 v0, v0, v0
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; GFX8-NEXT: v_mul_f32_e32 v0, v0, v0
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; GFX8-NEXT: v_mul_f32_e32 v0, v0, v0
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; GFX8-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
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; GFX8-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
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; GFX8-NEXT: v_rcp_f32_e32 v3, v1
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; GFX8-NEXT: v_fma_f32 v4, -v1, v3, 1.0
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; GFX8-NEXT: v_fma_f32 v3, v4, v3, v3
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; GFX8-NEXT: v_mul_f32_e32 v4, v2, v3
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; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v2
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; GFX8-NEXT: v_fma_f32 v4, v5, v3, v4
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; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v2
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; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4
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; GFX8-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
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; GFX8-NEXT: s_setpc_b64 s[30:31]
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%res = call float @llvm.powi.f32(float %l, i32 -128)
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ret float %res
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}
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; FIXME: f64 broken
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; define double @v_powi_f64(double %l, i32 %r) {
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; %res = call double @llvm.powi.f64(double %l, i32 %r)
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; ret double %res
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; }
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declare half @llvm.powi.f16(half, i32) #0
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declare float @llvm.powi.f32(float, i32) #0
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declare double @llvm.powi.f64(double, i32) #0
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attributes #0 = { nounwind readnone speculatable willreturn }
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