forked from OSchip/llvm-project
[NVPTX] Fix case where a sext load of an i1 type may produce an
ld.u1 instead of an ld.u8. llvm-svn: 182924
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@ -205,7 +205,8 @@ SDNode *NVPTXDAGToDAGISel::SelectLoad(SDNode *N) {
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// type is integer
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// Float : ISD::NON_EXTLOAD or ISD::EXTLOAD and the type is float
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MVT ScalarVT = SimpleVT.getScalarType();
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unsigned fromTypeWidth = ScalarVT.getSizeInBits();
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// Read at least 8 bits (predicates are stored as 8-bit values)
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unsigned fromTypeWidth = std::max(8U, ScalarVT.getSizeInBits());
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unsigned int fromType;
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if ((LD->getExtensionType() == ISD::SEXTLOAD))
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fromType = NVPTX::PTXLdStInstCode::Signed;
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@ -430,7 +431,8 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadVector(SDNode *N) {
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// type is integer
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// Float : ISD::NON_EXTLOAD or ISD::EXTLOAD and the type is float
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MVT ScalarVT = SimpleVT.getScalarType();
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unsigned FromTypeWidth = ScalarVT.getSizeInBits();
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// Read at least 8 bits (predicates are stored as 8-bit values)
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unsigned FromTypeWidth = std::max(8U, ScalarVT.getSizeInBits());
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unsigned int FromType;
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// The last operand holds the original LoadSDNode::getExtensionType() value
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unsigned ExtensionType = cast<ConstantSDNode>(
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@ -0,0 +1,14 @@
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
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define void @main(i1* %a1, i32 %a2, i32* %arg3) {
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; CHECK: ld.u8
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; CHECK-NOT: ld.u1
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%t1 = getelementptr i1* %a1, i32 %a2
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%t2 = load i1* %t1
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%t3 = sext i1 %t2 to i32
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store i32 %t3, i32* %arg3
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ret void
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}
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