forked from OSchip/llvm-project
[AArch64][GlobalISel] Teach tryOptSelect to handle G_ICMP
This teaches `tryOptSelect` to handle folding G_ICMP, and removes the requirement that the G_SELECT we're dealing with is floating point. Some refactoring to make this work nicely as well: - Factor out the scalar case from the selection code for G_ICMP into `emitIntegerCompare`. - Make `tryOptCMN` return a MachineInstr* instead of a bool. - Make `tryOptCMN` not modify the instruction being selected. - Factor out the CMN emission into `emitCMN` for readability. By doing this this way, we can get all of the compare selection optimizations in select emission. Differential Revision: https://reviews.llvm.org/D64084 llvm-svn: 364961
This commit is contained in:
Jessica Paquette
parent
a700436323
commit
99316043bb
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@ -116,6 +116,11 @@ private:
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MachineInstr *emitVectorConcat(Optional<Register> Dst, Register Op1,
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Register Op2,
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MachineIRBuilder &MIRBuilder) const;
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MachineInstr *emitIntegerCompare(MachineOperand &LHS, MachineOperand &RHS,
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MachineOperand &Predicate,
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MachineIRBuilder &MIRBuilder) const;
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MachineInstr *emitCMN(MachineOperand &LHS, MachineOperand &RHS,
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MachineIRBuilder &MIRBuilder) const;
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MachineInstr *emitExtractVectorElt(Optional<Register> DstReg,
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const RegisterBank &DstRB, LLT ScalarTy,
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Register VecReg, unsigned LaneIdx,
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@ -180,7 +185,9 @@ private:
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bool tryOptVectorShuffle(MachineInstr &I) const;
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bool tryOptVectorDup(MachineInstr &MI) const;
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bool tryOptSelect(MachineInstr &MI) const;
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bool tryOptCMN(MachineInstr &MI) const;
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MachineInstr *tryOptCMN(MachineOperand &LHS, MachineOperand &RHS,
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MachineOperand &Predicate,
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MachineIRBuilder &MIRBuilder) const;
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const AArch64TargetMachine &TM;
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const AArch64Subtarget &STI;
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@ -1818,12 +1825,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
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const Register TReg = I.getOperand(2).getReg();
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const Register FReg = I.getOperand(3).getReg();
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// If we have a floating-point result, then we should use a floating point
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// select instead of an integer select.
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bool IsFP = (RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() !=
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AArch64::GPRRegBankID);
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if (IsFP && tryOptSelect(I))
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if (tryOptSelect(I))
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return true;
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Register CSelOpc = selectSelectOpc(I, MRI, RBI);
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@ -1855,46 +1857,12 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
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return false;
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}
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unsigned CmpOpc = 0;
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Register ZReg;
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// Check if this compare can be represented as a cmn, and perform any
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// necessary transformations to do so.
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if (tryOptCMN(I))
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return true;
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LLT CmpTy = MRI.getType(I.getOperand(2).getReg());
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if (CmpTy == LLT::scalar(32)) {
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CmpOpc = AArch64::SUBSWrr;
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ZReg = AArch64::WZR;
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} else if (CmpTy == LLT::scalar(64) || CmpTy.isPointer()) {
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CmpOpc = AArch64::SUBSXrr;
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ZReg = AArch64::XZR;
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} else {
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return false;
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}
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// Try to match immediate forms.
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auto ImmFns = selectArithImmed(I.getOperand(3));
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if (ImmFns)
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CmpOpc = CmpOpc == AArch64::SUBSWrr ? AArch64::SUBSWri : AArch64::SUBSXri;
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auto CmpMI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(CmpOpc))
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.addDef(ZReg)
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.addUse(I.getOperand(2).getReg());
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// If we matched a valid constant immediate, add those operands.
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if (ImmFns) {
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for (auto &RenderFn : *ImmFns)
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RenderFn(CmpMI);
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} else {
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CmpMI.addUse(I.getOperand(3).getReg());
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}
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MachineIRBuilder MIRBuilder(I);
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if (!emitIntegerCompare(I.getOperand(2), I.getOperand(3), I.getOperand(1),
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MIRBuilder))
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return false;
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emitCSetForICMP(I.getOperand(0).getReg(), I.getOperand(1).getPredicate(),
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MIRBuilder);
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constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI);
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MIRBuilder);
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I.eraseFromParent();
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return true;
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}
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@ -2803,6 +2771,78 @@ getInsertVecEltOpInfo(const RegisterBank &RB, unsigned EltSize) {
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return std::make_pair(Opc, SubregIdx);
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}
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MachineInstr *
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AArch64InstructionSelector::emitCMN(MachineOperand &LHS, MachineOperand &RHS,
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MachineIRBuilder &MIRBuilder) const {
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assert(LHS.isReg() && RHS.isReg() && "Expected LHS and RHS to be registers!");
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MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
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static const unsigned OpcTable[2][2]{{AArch64::ADDSXrr, AArch64::ADDSXri},
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{AArch64::ADDSWrr, AArch64::ADDSWri}};
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bool Is32Bit = (MRI.getType(LHS.getReg()).getSizeInBits() == 32);
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auto ImmFns = selectArithImmed(RHS);
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unsigned Opc = OpcTable[Is32Bit][ImmFns.hasValue()];
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Register ZReg = Is32Bit ? AArch64::WZR : AArch64::XZR;
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auto CmpMI = MIRBuilder.buildInstr(Opc, {ZReg}, {LHS.getReg()});
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// If we matched a valid constant immediate, add those operands.
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if (ImmFns) {
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for (auto &RenderFn : *ImmFns)
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RenderFn(CmpMI);
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} else {
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CmpMI.addUse(RHS.getReg());
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}
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constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI);
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return &*CmpMI;
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}
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MachineInstr *AArch64InstructionSelector::emitIntegerCompare(
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MachineOperand &LHS, MachineOperand &RHS, MachineOperand &Predicate,
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MachineIRBuilder &MIRBuilder) const {
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assert(LHS.isReg() && RHS.isReg() && "Expected LHS and RHS to be registers!");
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MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
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// Fold the compare into a CMN if possible.
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MachineInstr *Cmn = tryOptCMN(LHS, RHS, Predicate, MIRBuilder);
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if (Cmn)
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return Cmn;
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// Can't fold into a CMN. Just emit a normal compare.
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unsigned CmpOpc = 0;
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Register ZReg;
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LLT CmpTy = MRI.getType(LHS.getReg());
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assert(CmpTy.isScalar() || CmpTy.isPointer() && "Expected scalar or pointer");
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if (CmpTy == LLT::scalar(32)) {
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CmpOpc = AArch64::SUBSWrr;
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ZReg = AArch64::WZR;
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} else if (CmpTy == LLT::scalar(64) || CmpTy.isPointer()) {
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CmpOpc = AArch64::SUBSXrr;
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ZReg = AArch64::XZR;
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} else {
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return nullptr;
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}
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// Try to match immediate forms.
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auto ImmFns = selectArithImmed(RHS);
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if (ImmFns)
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CmpOpc = CmpOpc == AArch64::SUBSWrr ? AArch64::SUBSWri : AArch64::SUBSXri;
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auto CmpMI = MIRBuilder.buildInstr(CmpOpc).addDef(ZReg).addUse(LHS.getReg());
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// If we matched a valid constant immediate, add those operands.
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if (ImmFns) {
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for (auto &RenderFn : *ImmFns)
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RenderFn(CmpMI);
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} else {
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CmpMI.addUse(RHS.getReg());
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}
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// Make sure that we can constrain the compare that we emitted.
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constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI);
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return &*CmpMI;
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}
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MachineInstr *AArch64InstructionSelector::emitVectorConcat(
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Optional<Register> Dst, Register Op1, Register Op2,
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MachineIRBuilder &MIRBuilder) const {
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@ -2954,33 +2994,47 @@ bool AArch64InstructionSelector::tryOptSelect(MachineInstr &I) const {
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}
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// Is the condition defined by a compare?
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// TODO: Handle G_ICMP.
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if (!CondDef || CondDef->getOpcode() != TargetOpcode::G_FCMP)
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if (!CondDef)
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return false;
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unsigned CondOpc = CondDef->getOpcode();
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if (CondOpc != TargetOpcode::G_ICMP && CondOpc != TargetOpcode::G_FCMP)
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return false;
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// Get the condition code for the select.
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AArch64CC::CondCode CondCode;
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AArch64CC::CondCode CondCode2;
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changeFCMPPredToAArch64CC(
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(CmpInst::Predicate)CondDef->getOperand(1).getPredicate(), CondCode,
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CondCode2);
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if (CondOpc == TargetOpcode::G_ICMP) {
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CondCode = changeICMPPredToAArch64CC(
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(CmpInst::Predicate)CondDef->getOperand(1).getPredicate());
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if (!emitIntegerCompare(CondDef->getOperand(2), CondDef->getOperand(3),
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CondDef->getOperand(1), MIB)) {
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LLVM_DEBUG(dbgs() << "Couldn't emit compare for select!\n");
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return false;
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}
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} else {
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// Get the condition code for the select.
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AArch64CC::CondCode CondCode2;
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changeFCMPPredToAArch64CC(
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(CmpInst::Predicate)CondDef->getOperand(1).getPredicate(), CondCode,
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CondCode2);
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// changeFCMPPredToAArch64CC sets CondCode2 to AL when we require two
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// instructions to emit the comparison.
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// TODO: Handle FCMP_UEQ and FCMP_ONE. After that, this check will be
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// unnecessary.
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if (CondCode2 != AArch64CC::AL)
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return false;
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// changeFCMPPredToAArch64CC sets CondCode2 to AL when we require two
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// instructions to emit the comparison.
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// TODO: Handle FCMP_UEQ and FCMP_ONE. After that, this check will be
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// unnecessary.
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if (CondCode2 != AArch64CC::AL)
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return false;
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// Make sure we'll be able to select the compare.
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unsigned CmpOpc = selectFCMPOpc(*CondDef, MRI);
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if (!CmpOpc)
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return false;
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// Make sure we'll be able to select the compare.
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unsigned CmpOpc = selectFCMPOpc(*CondDef, MRI);
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if (!CmpOpc)
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return false;
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// Emit a new compare.
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auto Cmp = MIB.buildInstr(CmpOpc, {}, {CondDef->getOperand(2).getReg()});
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if (CmpOpc != AArch64::FCMPSri && CmpOpc != AArch64::FCMPDri)
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Cmp.addUse(CondDef->getOperand(3).getReg());
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// Emit a new compare.
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auto Cmp = MIB.buildInstr(CmpOpc, {}, {CondDef->getOperand(2).getReg()});
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if (CmpOpc != AArch64::FCMPSri && CmpOpc != AArch64::FCMPDri)
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Cmp.addUse(CondDef->getOperand(3).getReg());
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constrainSelectedInstRegOperands(*Cmp, TII, TRI, RBI);
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}
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// Emit the select.
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unsigned CSelOpc = selectSelectOpc(I, MRI, RBI);
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@ -2988,15 +3042,17 @@ bool AArch64InstructionSelector::tryOptSelect(MachineInstr &I) const {
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MIB.buildInstr(CSelOpc, {I.getOperand(0).getReg()},
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{I.getOperand(2).getReg(), I.getOperand(3).getReg()})
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.addImm(CondCode);
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constrainSelectedInstRegOperands(*Cmp, TII, TRI, RBI);
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constrainSelectedInstRegOperands(*CSel, TII, TRI, RBI);
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I.eraseFromParent();
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return true;
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}
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bool AArch64InstructionSelector::tryOptCMN(MachineInstr &I) const {
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assert(I.getOpcode() == TargetOpcode::G_ICMP && "Expected G_ICMP");
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MachineIRBuilder MIRBuilder(I);
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MachineInstr *
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AArch64InstructionSelector::tryOptCMN(MachineOperand &LHS, MachineOperand &RHS,
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MachineOperand &Predicate,
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MachineIRBuilder &MIRBuilder) const {
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assert(LHS.isReg() && RHS.isReg() && Predicate.isPredicate() &&
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"Unexpected MachineOperand");
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MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
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// We want to find this sort of thing:
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// x = G_SUB 0, y
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@ -3047,11 +3103,14 @@ bool AArch64InstructionSelector::tryOptCMN(MachineInstr &I) const {
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};
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// Check if the RHS or LHS of the G_ICMP is defined by a SUB
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MachineInstr *LHSDef = FindDef(I.getOperand(2).getReg());
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MachineInstr *RHSDef = FindDef(I.getOperand(3).getReg());
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const AArch64CC::CondCode CC = changeICMPPredToAArch64CC(
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(CmpInst::Predicate)I.getOperand(1).getPredicate());
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MachineInstr *LHSDef = FindDef(LHS.getReg());
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MachineInstr *RHSDef = FindDef(RHS.getReg());
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const AArch64CC::CondCode CC =
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changeICMPPredToAArch64CC((CmpInst::Predicate)Predicate.getPredicate());
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bool DidFold = false;
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MachineOperand CMNLHS = LHS;
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MachineOperand CMNRHS = RHS;
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if (IsCMN(LHSDef, CC)) {
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// We're doing this:
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//
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@ -3063,7 +3122,7 @@ bool AArch64InstructionSelector::tryOptCMN(MachineInstr &I) const {
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// Update the G_ICMP:
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//
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// G_ICMP y, z
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I.getOperand(2).setReg(LHSDef->getOperand(2).getReg());
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CMNLHS = LHSDef->getOperand(2);
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DidFold = true;
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} else if (IsCMN(RHSDef, CC)) {
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// Same idea here, but with the RHS of the compare instead:
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@ -3076,39 +3135,13 @@ bool AArch64InstructionSelector::tryOptCMN(MachineInstr &I) const {
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// Update the G_ICMP:
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//
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// G_ICMP z, y
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I.getOperand(3).setReg(RHSDef->getOperand(2).getReg());
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CMNRHS = RHSDef->getOperand(2);
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DidFold = true;
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}
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if (DidFold) {
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// We can fold. Emit a CMN.
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static const unsigned OpcTable[2][2]{{AArch64::ADDSXrr, AArch64::ADDSXri},
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{AArch64::ADDSWrr, AArch64::ADDSWri}};
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bool Is32Bit =
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(MRI.getType(I.getOperand(2).getReg()).getSizeInBits() == 32);
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auto ImmFns = selectArithImmed(I.getOperand(3));
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unsigned Opc = OpcTable[Is32Bit][ImmFns.hasValue()];
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Register ZReg = Is32Bit ? AArch64::WZR : AArch64::XZR;
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auto CmpMI = MIRBuilder.buildInstr(Opc, {ZReg}, {I.getOperand(2).getReg()});
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// If we matched a valid constant immediate, add those operands.
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if (ImmFns) {
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for (auto &RenderFn : *ImmFns)
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RenderFn(CmpMI);
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} else {
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CmpMI.addUse(I.getOperand(3).getReg());
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}
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constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI);
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// Add a CSet after the CMN.
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emitCSetForICMP(I.getOperand(0).getReg(), I.getOperand(1).getPredicate(),
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MIRBuilder);
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I.eraseFromParent();
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}
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return DidFold;
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if (DidFold)
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return emitCMN(CMNLHS, CMNRHS, MIRBuilder);
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return nullptr;
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}
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bool AArch64InstructionSelector::tryOptVectorDup(MachineInstr &I) const {
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@ -8,7 +8,6 @@
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#
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# Also verify that, for now:
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#
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# - We only support doing this with G_FCMP.
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# - We only support condition flags that require a single instruction.
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#
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@ -65,11 +64,7 @@ body: |
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; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
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; CHECK: $wzr = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[CSINCWr]]
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; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
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; CHECK: $wzr = ANDSWri [[COPY3]], 0, implicit-def $nzcv
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; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv
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; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 0, implicit $nzcv
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; CHECK: $s0 = COPY [[FCSELSrrr]]
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; CHECK: RET_ReallyLR implicit $s0
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%0:gpr(s32) = COPY $w0
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@ -0,0 +1,68 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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#
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# Verify that we can fold compares into integer selects.
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#
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# This is an integer version of fold-fp-select.mir.
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#
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...
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---
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name: eq
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $w1
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; CHECK-LABEL: name: eq
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; CHECK: liveins: $w0, $w1
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; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
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; CHECK: $wzr = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv
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; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY1]], 0, implicit $nzcv
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; CHECK: $w0 = COPY [[CSELWr]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(s32) = COPY $w0
|
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%1:gpr(s32) = COPY $w1
|
||||
%2:gpr(s32) = G_CONSTANT i32 0
|
||||
%5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2
|
||||
%3:gpr(s1) = G_TRUNC %5(s32)
|
||||
%4:gpr(s32) = G_SELECT %3(s1), %2, %1
|
||||
$w0 = COPY %4(s32)
|
||||
RET_ReallyLR implicit $w0
|
||||
|
||||
...
|
||||
---
|
||||
name: using_fcmp
|
||||
alignment: 2
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $s0, $w0, $w1
|
||||
|
||||
; CHECK-LABEL: name: using_fcmp
|
||||
; CHECK: liveins: $s0, $w0, $w1
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
|
||||
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
|
||||
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
|
||||
; CHECK: FCMPSri [[COPY1]], implicit-def $nzcv
|
||||
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY]], 0, implicit $nzcv
|
||||
; CHECK: $w0 = COPY [[CSELWr]]
|
||||
; CHECK: RET_ReallyLR implicit $w0
|
||||
%1:gpr(s32) = COPY $w1
|
||||
%2:fpr(s32) = COPY $s0
|
||||
%3:fpr(s32) = G_FCONSTANT float 0.000000e+00
|
||||
%6:gpr(s32) = G_CONSTANT i32 0
|
||||
%7:gpr(s32) = G_FCMP floatpred(oeq), %2(s32), %3
|
||||
%4:gpr(s1) = G_TRUNC %7(s32)
|
||||
%5:gpr(s32) = G_SELECT %4(s1), %6, %1
|
||||
$w0 = COPY %5(s32)
|
||||
RET_ReallyLR implicit $w0
|
||||
|
||||
...
|
||||
|
|
@ -30,8 +30,6 @@ body: |
|
|||
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
|
||||
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
|
||||
; CHECK: $wzr = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
|
||||
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
|
||||
; CHECK: $wzr = ANDSWri [[CSINCWr]], 0, implicit-def $nzcv
|
||||
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 1, implicit $nzcv
|
||||
; CHECK: $w0 = COPY [[CSELWr]]
|
||||
; CHECK: RET_ReallyLR implicit $w0
|
||||
|
|
@ -64,8 +62,6 @@ body: |
|
|||
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
|
||||
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
|
||||
; CHECK: $wzr = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
|
||||
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
|
||||
; CHECK: $wzr = ANDSWri [[CSINCWr]], 0, implicit-def $nzcv
|
||||
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 1, implicit $nzcv
|
||||
; CHECK: $w0 = COPY [[CSELWr]]
|
||||
; CHECK: RET_ReallyLR implicit $w0
|
||||
|
|
@ -99,9 +95,7 @@ body: |
|
|||
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
|
||||
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[MOVi32imm]], [[COPY1]], implicit-def $nzcv
|
||||
; CHECK: $wzr = SUBSWrr [[COPY]], [[SUBSWrr]], implicit-def $nzcv
|
||||
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
|
||||
; CHECK: $wzr = ANDSWri [[CSINCWr]], 0, implicit-def $nzcv
|
||||
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 1, implicit $nzcv
|
||||
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 11, implicit $nzcv
|
||||
; CHECK: $w0 = COPY [[CSELWr]]
|
||||
; CHECK: RET_ReallyLR implicit $w0
|
||||
%0:gpr(s32) = COPY $w0
|
||||
|
|
@ -134,9 +128,7 @@ body: |
|
|||
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
|
||||
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[MOVi32imm]], [[COPY]], implicit-def $nzcv
|
||||
; CHECK: $wzr = SUBSWrr [[SUBSWrr]], [[COPY1]], implicit-def $nzcv
|
||||
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
|
||||
; CHECK: $wzr = ANDSWri [[CSINCWr]], 0, implicit-def $nzcv
|
||||
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 1, implicit $nzcv
|
||||
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 11, implicit $nzcv
|
||||
; CHECK: $w0 = COPY [[CSELWr]]
|
||||
; CHECK: RET_ReallyLR implicit $w0
|
||||
%0:gpr(s32) = COPY $w0
|
||||
|
|
@ -168,8 +160,6 @@ body: |
|
|||
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 0
|
||||
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
|
||||
; CHECK: $xzr = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
|
||||
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
|
||||
; CHECK: $wzr = ANDSWri [[CSINCWr]], 0, implicit-def $nzcv
|
||||
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 1, implicit $nzcv
|
||||
; CHECK: $x0 = COPY [[CSELXr]]
|
||||
; CHECK: RET_ReallyLR implicit $x0
|
||||
|
|
@ -202,8 +192,6 @@ body: |
|
|||
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 0
|
||||
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
|
||||
; CHECK: $xzr = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
|
||||
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
|
||||
; CHECK: $wzr = ANDSWri [[CSINCWr]], 0, implicit-def $nzcv
|
||||
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 1, implicit $nzcv
|
||||
; CHECK: $x0 = COPY [[CSELXr]]
|
||||
; CHECK: RET_ReallyLR implicit $x0
|
||||
|
|
@ -237,9 +225,7 @@ body: |
|
|||
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
|
||||
; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[MOVi64imm]], [[COPY1]], implicit-def $nzcv
|
||||
; CHECK: $xzr = SUBSXrr [[COPY]], [[SUBSXrr]], implicit-def $nzcv
|
||||
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
|
||||
; CHECK: $wzr = ANDSWri [[CSINCWr]], 0, implicit-def $nzcv
|
||||
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 1, implicit $nzcv
|
||||
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 11, implicit $nzcv
|
||||
; CHECK: $x0 = COPY [[CSELXr]]
|
||||
; CHECK: RET_ReallyLR implicit $x0
|
||||
%0:gpr(s64) = COPY $x0
|
||||
|
|
@ -272,9 +258,7 @@ body: |
|
|||
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
|
||||
; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[MOVi64imm]], [[COPY]], implicit-def $nzcv
|
||||
; CHECK: $xzr = SUBSXrr [[SUBSXrr]], [[COPY1]], implicit-def $nzcv
|
||||
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
|
||||
; CHECK: $wzr = ANDSWri [[CSINCWr]], 0, implicit-def $nzcv
|
||||
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 1, implicit $nzcv
|
||||
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 11, implicit $nzcv
|
||||
; CHECK: $x0 = COPY [[CSELXr]]
|
||||
; CHECK: RET_ReallyLR implicit $x0
|
||||
%0:gpr(s64) = COPY $x0
|
||||
|
|
|
|||
Loading…
Reference in New Issue