maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[RISCV] Make TuneSiFive7 depend on TuneNoDefaultUnroll instead of listing it for every SiFive7 CPU

This commit is contained in:
Craig Topper 2022-07-14 15:13:02 -07:00
parent 61891748f5
commit 9913ea490a
1 changed files with 7 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
llvm/lib/Target/RISCV/RISCV.td
View File

@ -465,7 +465,8 @@ def TuneNoDefaultUnroll
"Disable default unroll preference.">;
def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
"SiFive 7-Series processors">;
"SiFive 7-Series processors",
[TuneNoDefaultUnroll]>;
//===----------------------------------------------------------------------===//
// Named operands for CSR instructions.
@ -499,9 +500,9 @@ def : ProcessorModel<"rocket-rv32", RocketModel, []>;
def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>;
def : ProcessorModel<"sifive-7-rv32", SiFive7Model, [],
[TuneSiFive7, TuneNoDefaultUnroll]>;
[TuneSiFive7]>;
def : ProcessorModel<"sifive-7-rv64", SiFive7Model, [Feature64Bit],
[TuneSiFive7, TuneNoDefaultUnroll]>;
[TuneSiFive7]>;
def : ProcessorModel<"sifive-e20", RocketModel, [FeatureStdExtM,
FeatureStdExtC]>;
@ -528,7 +529,7 @@ def : ProcessorModel<"sifive-e76", SiFive7Model, [FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtC],
[TuneSiFive7, TuneNoDefaultUnroll]>;
[TuneSiFive7]>;
def : ProcessorModel<"sifive-s21", RocketModel, [Feature64Bit,
FeatureStdExtM,
@ -553,7 +554,7 @@ def : ProcessorModel<"sifive-s76", SiFive7Model, [Feature64Bit,
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC],
[TuneSiFive7, TuneNoDefaultUnroll]>;
[TuneSiFive7]>;
def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
FeatureStdExtM,
@ -568,7 +569,7 @@ def : ProcessorModel<"sifive-u74", SiFive7Model, [Feature64Bit,
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC],
[TuneSiFive7, TuneNoDefaultUnroll]>;
[TuneSiFive7]>;
//===----------------------------------------------------------------------===//
// Define the RISC-V target.