maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[BOLT][NFC] Fix white space 

(cherry picked from FBD16473918)
This commit is contained in:
Maksim Panchenko 2019-07-24 17:54:14 -07:00
parent 744a2417dd
commit 98fdba2cc7
14 changed files with 189 additions and 189 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

42
bolt/src/MCPlusBuilder.cpp
View File

@ -263,9 +263,9 @@ MCPlusBuilder::printAnnotations(const MCInst &Inst, raw_ostream &OS) const {
bool MCPlusBuilder::evaluateBranch(const MCInst &Inst, uint64_t Addr,
uint64_t Size, uint64_t &Target) const {
return Analysis->evaluateBranch(Inst, Addr, Size, Target);
}
}
void MCPlusBuilder::getClobberedRegs(const MCInst &Inst,
void MCPlusBuilder::getClobberedRegs(const MCInst &Inst,
BitVector &Regs) const {
if (isPrefix(Inst) || isCFI(Inst))
return;
@ -282,9 +282,9 @@ bool MCPlusBuilder::evaluateBranch(const MCInst &Inst, uint64_t Addr,
assert(Operand.isReg());
Regs |= getAliases(Operand.getReg(), /*OnlySmaller=*/false);
}
}
}
void MCPlusBuilder::getTouchedRegs(const MCInst &Inst,
void MCPlusBuilder::getTouchedRegs(const MCInst &Inst,
BitVector &Regs) const {
if (isPrefix(Inst) || isCFI(Inst))
return;
@ -305,9 +305,9 @@ bool MCPlusBuilder::evaluateBranch(const MCInst &Inst, uint64_t Addr,
continue;
Regs |= getAliases(Inst.getOperand(I).getReg(), /*OnlySmaller=*/false);
}
}
}
void MCPlusBuilder::getWrittenRegs(const MCInst &Inst,
void MCPlusBuilder::getWrittenRegs(const MCInst &Inst,
BitVector &Regs) const {
if (isPrefix(Inst) || isCFI(Inst))
return;
@ -324,9 +324,9 @@ bool MCPlusBuilder::evaluateBranch(const MCInst &Inst, uint64_t Addr,
assert(Operand.isReg());
Regs |= getAliases(Operand.getReg(), /*OnlySmaller=*/true);
}
}
}
void MCPlusBuilder::getUsedRegs(const MCInst &Inst, BitVector &Regs) const {
void MCPlusBuilder::getUsedRegs(const MCInst &Inst, BitVector &Regs) const {
if (isPrefix(Inst) || isCFI(Inst))
return;
@ -342,14 +342,14 @@ bool MCPlusBuilder::evaluateBranch(const MCInst &Inst, uint64_t Addr,
continue;
Regs |= getAliases(Inst.getOperand(I).getReg(), /*OnlySmaller=*/true);
}
}
}
bool MCPlusBuilder::hasDefOfPhysReg(const MCInst &MI, unsigned Reg) const {
bool MCPlusBuilder::hasDefOfPhysReg(const MCInst &MI, unsigned Reg) const {
const auto &InstInfo = Info->get(MI.getOpcode());
return InstInfo.hasDefOfPhysReg(MI, Reg, *RegInfo);
}
}
bool MCPlusBuilder::hasUseOfPhysReg(const MCInst &MI, unsigned Reg) const {
bool MCPlusBuilder::hasUseOfPhysReg(const MCInst &MI, unsigned Reg) const {
const auto &InstInfo = Info->get(MI.getOpcode());
for (int I = InstInfo.NumDefs; I < InstInfo.NumOperands; ++I)
if (MI.getOperand(I).isReg() &&
@ -360,10 +360,10 @@ bool MCPlusBuilder::evaluateBranch(const MCInst &Inst, uint64_t Addr,
if (*ImpUses == Reg || RegInfo->isSubRegister(Reg, *ImpUses))
return true;
return false;
}
}
const BitVector &
MCPlusBuilder::getAliases(MCPhysReg Reg,
const BitVector &
MCPlusBuilder::getAliases(MCPhysReg Reg,
bool OnlySmaller) const {
// AliasMap caches a mapping of registers to the set of registers that
// alias (are sub or superregs of itself, including itself).
@ -427,10 +427,10 @@ bool MCPlusBuilder::evaluateBranch(const MCInst &Inst, uint64_t Addr,
if (OnlySmaller)
return AliasMap[Reg];
return AliasMap[SuperReg[Reg]];
}
}
uint8_t
MCPlusBuilder::getRegSize(MCPhysReg Reg) const {
uint8_t
MCPlusBuilder::getRegSize(MCPhysReg Reg) const {
// SizeMap caches a mapping of registers to their sizes
static std::vector<uint8_t> SizeMap;
@ -447,9 +447,9 @@ bool MCPlusBuilder::evaluateBranch(const MCInst &Inst, uint64_t Addr,
}
return SizeMap[Reg];
}
}
bool MCPlusBuilder::setOperandToSymbolRef(MCInst &Inst, int OpNum,
bool MCPlusBuilder::setOperandToSymbolRef(MCInst &Inst, int OpNum,
const MCSymbol *Symbol,
int64_t Addend, MCContext *Ctx,
uint64_t RelType) const {
@ -466,4 +466,4 @@ bool MCPlusBuilder::evaluateBranch(const MCInst &Inst, uint64_t Addr,
}
Inst.getOperand(OpNum) = Operand;
return true;
}
}