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[BOLT][NFC] Fix white space 

(cherry picked from FBD16473918)
This commit is contained in:
Maksim Panchenko 2019-07-24 17:54:14 -07:00
parent 744a2417dd
commit 98fdba2cc7
14 changed files with 189 additions and 189 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
bolt/src/BinaryFunction.h
View File

@ -1838,7 +1838,7 @@ public:
// Register our island at global namespace
Symbol = BC.getOrCreateGlobalSymbol(Address, "ISLANDat");
// Internal bookkeeping
const auto Offset = Address - getAddress();
assert((!IslandOffsets.count(Offset) || IslandOffsets[Offset] == Symbol) &&

6
bolt/src/DWARFRewriter.h
View File

@ -33,11 +33,11 @@ class DWARFRewriter {
SectionPatchersType &SectionPatchers;
SimpleBinaryPatcher *DebugInfoPatcher{nullptr};
std::mutex DebugInfoPatcherMutex;
DebugAbbrevPatcher *AbbrevPatcher{nullptr};
std::mutex AbbrevPatcherMutex;
/// Stores and serializes information that will be put into the .debug_ranges
@ -76,7 +76,7 @@ class DWARFRewriter {
/// Abbreviations that were converted to use DW_AT_ranges.
std::set<const DWARFAbbreviationDeclaration *> ConvertedRangesAbbrevs;
/// DIEs with abbrevs that were not converted to DW_AT_ranges.
/// We only update those when all DIEs have been processed to guarantee that
/// the abbrev (which is shared) is intact.

2
bolt/src/DebugData.cpp
View File

@ -172,7 +172,7 @@ uint64_t DebugLocWriter::addList(const DWARFDebugLoc::LocationList &LocList) {
// unique and correct offsets in patches.
std::lock_guard<std::mutex> Lock(WriterMutex);
const auto EntryOffset = SectionOffset;
for (const auto &Entry : LocList.Entries) {
Writer->writeLE64(Entry.Begin);
Writer->writeLE64(Entry.End);

2
bolt/src/Exceptions.cpp
View File

@ -364,7 +364,7 @@ void BinaryFunction::parseLSDA(ArrayRef<uint8_t> LSDASectionData,
void BinaryFunction::updateEHRanges() {
if (getSize() == 0)
return;
assert(CurrentState == State::CFG_Finalized && "unexpected state");
// Build call sites table.

342
bolt/src/MCPlusBuilder.cpp
View File

@ -263,207 +263,207 @@ MCPlusBuilder::printAnnotations(const MCInst &Inst, raw_ostream &OS) const {
bool MCPlusBuilder::evaluateBranch(const MCInst &Inst, uint64_t Addr,
uint64_t Size, uint64_t &Target) const {
return Analysis->evaluateBranch(Inst, Addr, Size, Target);
}
}
void MCPlusBuilder::getClobberedRegs(const MCInst &Inst,
BitVector &Regs) const {
if (isPrefix(Inst) || isCFI(Inst))
return;
const auto &InstInfo = Info->get(Inst.getOpcode());
const auto *ImplicitDefs = InstInfo.getImplicitDefs();
for (unsigned I = 0, E = InstInfo.getNumImplicitDefs(); I != E; ++I) {
Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/false);
}
for (unsigned I = 0, E = InstInfo.getNumDefs(); I != E; ++I) {
const auto &Operand = Inst.getOperand(I);
assert(Operand.isReg());
Regs |= getAliases(Operand.getReg(), /*OnlySmaller=*/false);
}
}
void MCPlusBuilder::getTouchedRegs(const MCInst &Inst,
void MCPlusBuilder::getClobberedRegs(const MCInst &Inst,
BitVector &Regs) const {
if (isPrefix(Inst) || isCFI(Inst))
return;
if (isPrefix(Inst) || isCFI(Inst))
return;
const auto &InstInfo = Info->get(Inst.getOpcode());
const auto &InstInfo = Info->get(Inst.getOpcode());
const auto *ImplicitDefs = InstInfo.getImplicitDefs();
for (unsigned I = 0, E = InstInfo.getNumImplicitDefs(); I != E; ++I) {
Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/false);
}
const auto *ImplicitUses = InstInfo.getImplicitUses();
for (unsigned I = 0, E = InstInfo.getNumImplicitUses(); I != E; ++I) {
Regs |= getAliases(ImplicitUses[I], /*OnlySmaller=*/false);
}
for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) {
if (!Inst.getOperand(I).isReg())
continue;
Regs |= getAliases(Inst.getOperand(I).getReg(), /*OnlySmaller=*/false);
}
const auto *ImplicitDefs = InstInfo.getImplicitDefs();
for (unsigned I = 0, E = InstInfo.getNumImplicitDefs(); I != E; ++I) {
Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/false);
}
void MCPlusBuilder::getWrittenRegs(const MCInst &Inst,
BitVector &Regs) const {
if (isPrefix(Inst) || isCFI(Inst))
return;
for (unsigned I = 0, E = InstInfo.getNumDefs(); I != E; ++I) {
const auto &Operand = Inst.getOperand(I);
assert(Operand.isReg());
Regs |= getAliases(Operand.getReg(), /*OnlySmaller=*/false);
}
}
const auto &InstInfo = Info->get(Inst.getOpcode());
void MCPlusBuilder::getTouchedRegs(const MCInst &Inst,
BitVector &Regs) const {
if (isPrefix(Inst) || isCFI(Inst))
return;
const auto *ImplicitDefs = InstInfo.getImplicitDefs();
for (unsigned I = 0, E = InstInfo.getNumImplicitDefs(); I != E; ++I) {
Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/true);
}
const auto &InstInfo = Info->get(Inst.getOpcode());
for (unsigned I = 0, E = InstInfo.getNumDefs(); I != E; ++I) {
const auto &Operand = Inst.getOperand(I);
assert(Operand.isReg());
Regs |= getAliases(Operand.getReg(), /*OnlySmaller=*/true);
}
const auto *ImplicitDefs = InstInfo.getImplicitDefs();
for (unsigned I = 0, E = InstInfo.getNumImplicitDefs(); I != E; ++I) {
Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/false);
}
const auto *ImplicitUses = InstInfo.getImplicitUses();
for (unsigned I = 0, E = InstInfo.getNumImplicitUses(); I != E; ++I) {
Regs |= getAliases(ImplicitUses[I], /*OnlySmaller=*/false);
}
void MCPlusBuilder::getUsedRegs(const MCInst &Inst, BitVector &Regs) const {
if (isPrefix(Inst) || isCFI(Inst))
return;
for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) {
if (!Inst.getOperand(I).isReg())
continue;
Regs |= getAliases(Inst.getOperand(I).getReg(), /*OnlySmaller=*/false);
}
}
const auto &InstInfo = Info->get(Inst.getOpcode());
void MCPlusBuilder::getWrittenRegs(const MCInst &Inst,
BitVector &Regs) const {
if (isPrefix(Inst) || isCFI(Inst))
return;
const auto *ImplicitUses = InstInfo.getImplicitUses();
for (unsigned I = 0, E = InstInfo.getNumImplicitUses(); I != E; ++I) {
Regs |= getAliases(ImplicitUses[I], /*OnlySmaller=*/true);
}
const auto &InstInfo = Info->get(Inst.getOpcode());
for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) {
if (!Inst.getOperand(I).isReg())
continue;
Regs |= getAliases(Inst.getOperand(I).getReg(), /*OnlySmaller=*/true);
}
const auto *ImplicitDefs = InstInfo.getImplicitDefs();
for (unsigned I = 0, E = InstInfo.getNumImplicitDefs(); I != E; ++I) {
Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/true);
}
bool MCPlusBuilder::hasDefOfPhysReg(const MCInst &MI, unsigned Reg) const {
const auto &InstInfo = Info->get(MI.getOpcode());
return InstInfo.hasDefOfPhysReg(MI, Reg, *RegInfo);
for (unsigned I = 0, E = InstInfo.getNumDefs(); I != E; ++I) {
const auto &Operand = Inst.getOperand(I);
assert(Operand.isReg());
Regs |= getAliases(Operand.getReg(), /*OnlySmaller=*/true);
}
}
void MCPlusBuilder::getUsedRegs(const MCInst &Inst, BitVector &Regs) const {
if (isPrefix(Inst) || isCFI(Inst))
return;
const auto &InstInfo = Info->get(Inst.getOpcode());
const auto *ImplicitUses = InstInfo.getImplicitUses();
for (unsigned I = 0, E = InstInfo.getNumImplicitUses(); I != E; ++I) {
Regs |= getAliases(ImplicitUses[I], /*OnlySmaller=*/true);
}
bool MCPlusBuilder::hasUseOfPhysReg(const MCInst &MI, unsigned Reg) const {
const auto &InstInfo = Info->get(MI.getOpcode());
for (int I = InstInfo.NumDefs; I < InstInfo.NumOperands; ++I)
if (MI.getOperand(I).isReg() &&
RegInfo->isSubRegisterEq(Reg, MI.getOperand(I).getReg()))
for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) {
if (!Inst.getOperand(I).isReg())
continue;
Regs |= getAliases(Inst.getOperand(I).getReg(), /*OnlySmaller=*/true);
}
}
bool MCPlusBuilder::hasDefOfPhysReg(const MCInst &MI, unsigned Reg) const {
const auto &InstInfo = Info->get(MI.getOpcode());
return InstInfo.hasDefOfPhysReg(MI, Reg, *RegInfo);
}
bool MCPlusBuilder::hasUseOfPhysReg(const MCInst &MI, unsigned Reg) const {
const auto &InstInfo = Info->get(MI.getOpcode());
for (int I = InstInfo.NumDefs; I < InstInfo.NumOperands; ++I)
if (MI.getOperand(I).isReg() &&
RegInfo->isSubRegisterEq(Reg, MI.getOperand(I).getReg()))
return true;
if (const uint16_t *ImpUses = InstInfo.ImplicitUses)
for (; *ImpUses; ++ImpUses)
if (*ImpUses == Reg || RegInfo->isSubRegister(Reg, *ImpUses))
return true;
if (const uint16_t *ImpUses = InstInfo.ImplicitUses)
for (; *ImpUses; ++ImpUses)
if (*ImpUses == Reg || RegInfo->isSubRegister(Reg, *ImpUses))
return true;
return false;
}
return false;
}
const BitVector &
MCPlusBuilder::getAliases(MCPhysReg Reg,
bool OnlySmaller) const {
// AliasMap caches a mapping of registers to the set of registers that
// alias (are sub or superregs of itself, including itself).
static std::vector<BitVector> AliasMap;
static std::vector<MCPhysReg> SuperReg;
if (AliasMap.size() > 0) {
if (OnlySmaller)
return AliasMap[Reg];
return AliasMap[SuperReg[Reg]];
}
// Build alias map
for (MCPhysReg I = 0, E = RegInfo->getNumRegs(); I != E; ++I) {
BitVector BV(RegInfo->getNumRegs(), false);
BV.set(I);
AliasMap.emplace_back(std::move(BV));
SuperReg.emplace_back(I);
}
std::queue<MCPhysReg> Worklist;
// Propagate alias info upwards
for (MCPhysReg I = 0, E = RegInfo->getNumRegs(); I != E; ++I) {
Worklist.push(I);
}
while (!Worklist.empty()) {
MCPhysReg I = Worklist.front();
Worklist.pop();
for (MCSubRegIterator SI(I, RegInfo); SI.isValid(); ++SI) {
AliasMap[I] |= AliasMap[*SI];
}
for (MCSuperRegIterator SI(I, RegInfo); SI.isValid(); ++SI) {
Worklist.push(*SI);
}
}
// Propagate parent reg downwards
for (MCPhysReg I = 0, E = RegInfo->getNumRegs(); I != E; ++I) {
Worklist.push(I);
}
while (!Worklist.empty()) {
MCPhysReg I = Worklist.front();
Worklist.pop();
for (MCSubRegIterator SI(I, RegInfo); SI.isValid(); ++SI) {
SuperReg[*SI] = SuperReg[I];
Worklist.push(*SI);
}
}
DEBUG({
dbgs() << "Dumping reg alias table:\n";
for (MCPhysReg I = 0, E = RegInfo->getNumRegs(); I != E; ++I) {
dbgs() << "Reg " << I << ": ";
const BitVector &BV = AliasMap[SuperReg[I]];
int Idx = BV.find_first();
while (Idx != -1) {
dbgs() << Idx << " ";
Idx = BV.find_next(Idx);
}
dbgs() << "\n";
}
});
const BitVector &
MCPlusBuilder::getAliases(MCPhysReg Reg,
bool OnlySmaller) const {
// AliasMap caches a mapping of registers to the set of registers that
// alias (are sub or superregs of itself, including itself).
static std::vector<BitVector> AliasMap;
static std::vector<MCPhysReg> SuperReg;
if (AliasMap.size() > 0) {
if (OnlySmaller)
return AliasMap[Reg];
return AliasMap[SuperReg[Reg]];
}
uint8_t
MCPlusBuilder::getRegSize(MCPhysReg Reg) const {
// SizeMap caches a mapping of registers to their sizes
static std::vector<uint8_t> SizeMap;
if (SizeMap.size() > 0) {
return SizeMap[Reg];
// Build alias map
for (MCPhysReg I = 0, E = RegInfo->getNumRegs(); I != E; ++I) {
BitVector BV(RegInfo->getNumRegs(), false);
BV.set(I);
AliasMap.emplace_back(std::move(BV));
SuperReg.emplace_back(I);
}
std::queue<MCPhysReg> Worklist;
// Propagate alias info upwards
for (MCPhysReg I = 0, E = RegInfo->getNumRegs(); I != E; ++I) {
Worklist.push(I);
}
while (!Worklist.empty()) {
MCPhysReg I = Worklist.front();
Worklist.pop();
for (MCSubRegIterator SI(I, RegInfo); SI.isValid(); ++SI) {
AliasMap[I] |= AliasMap[*SI];
}
SizeMap = std::vector<uint8_t>(RegInfo->getNumRegs());
// Build size map
for (auto I = RegInfo->regclass_begin(), E = RegInfo->regclass_end(); I != E;
++I) {
for (MCPhysReg Reg : *I) {
SizeMap[Reg] = I->getSize();
for (MCSuperRegIterator SI(I, RegInfo); SI.isValid(); ++SI) {
Worklist.push(*SI);
}
}
// Propagate parent reg downwards
for (MCPhysReg I = 0, E = RegInfo->getNumRegs(); I != E; ++I) {
Worklist.push(I);
}
while (!Worklist.empty()) {
MCPhysReg I = Worklist.front();
Worklist.pop();
for (MCSubRegIterator SI(I, RegInfo); SI.isValid(); ++SI) {
SuperReg[*SI] = SuperReg[I];
Worklist.push(*SI);
}
}
DEBUG({
dbgs() << "Dumping reg alias table:\n";
for (MCPhysReg I = 0, E = RegInfo->getNumRegs(); I != E; ++I) {
dbgs() << "Reg " << I << ": ";
const BitVector &BV = AliasMap[SuperReg[I]];
int Idx = BV.find_first();
while (Idx != -1) {
dbgs() << Idx << " ";
Idx = BV.find_next(Idx);
}
dbgs() << "\n";
}
});
if (OnlySmaller)
return AliasMap[Reg];
return AliasMap[SuperReg[Reg]];
}
uint8_t
MCPlusBuilder::getRegSize(MCPhysReg Reg) const {
// SizeMap caches a mapping of registers to their sizes
static std::vector<uint8_t> SizeMap;
if (SizeMap.size() > 0) {
return SizeMap[Reg];
}
bool MCPlusBuilder::setOperandToSymbolRef(MCInst &Inst, int OpNum,
const MCSymbol *Symbol,
int64_t Addend, MCContext *Ctx,
uint64_t RelType) const {
MCOperand Operand;
if (!Addend) {
Operand = MCOperand::createExpr(getTargetExprFor(
Inst, MCSymbolRefExpr::create(Symbol, *Ctx), *Ctx, RelType));
} else {
Operand = MCOperand::createExpr(getTargetExprFor(
Inst,
MCBinaryExpr::createAdd(MCSymbolRefExpr::create(Symbol, *Ctx),
MCConstantExpr::create(Addend, *Ctx), *Ctx),
*Ctx, RelType));
SizeMap = std::vector<uint8_t>(RegInfo->getNumRegs());
// Build size map
for (auto I = RegInfo->regclass_begin(), E = RegInfo->regclass_end(); I != E;
++I) {
for (MCPhysReg Reg : *I) {
SizeMap[Reg] = I->getSize();
}
Inst.getOperand(OpNum) = Operand;
return true;
}
return SizeMap[Reg];
}
bool MCPlusBuilder::setOperandToSymbolRef(MCInst &Inst, int OpNum,
const MCSymbol *Symbol,
int64_t Addend, MCContext *Ctx,
uint64_t RelType) const {
MCOperand Operand;
if (!Addend) {
Operand = MCOperand::createExpr(getTargetExprFor(
Inst, MCSymbolRefExpr::create(Symbol, *Ctx), *Ctx, RelType));
} else {
Operand = MCOperand::createExpr(getTargetExprFor(
Inst,
MCBinaryExpr::createAdd(MCSymbolRefExpr::create(Symbol, *Ctx),
MCConstantExpr::create(Addend, *Ctx), *Ctx),
*Ctx, RelType));
}
Inst.getOperand(OpNum) = Operand;
return true;
}

6
bolt/src/MCPlusBuilder.h
View File

@ -44,7 +44,7 @@
namespace llvm {
namespace bolt {
/// Different types of indirect branches encountered during disassembly.
enum class IndirectBranchType : char {
UNKNOWN = 0, /// Unable to determine type.
@ -1503,7 +1503,7 @@ public:
MCSymbolRefExpr::create(Label, MCSymbolRefExpr::VK_None, *Ctx)));
return true;
}
/// Return annotation index matching the \p Name.
Optional<unsigned> getAnnotationIndex(StringRef Name) const {
auto AI = AnnotationNameIndexMap.find(Name);
@ -1675,7 +1675,7 @@ public:
bool removeAnnotation(MCInst &Inst, unsigned Index);
/// Remove annotation associated with \p Name.
///
///
/// Return true if the annotation was removed, false if the annotation
/// was not present.
bool removeAnnotation(MCInst &Inst, StringRef Name) {

2
bolt/src/Passes/BinaryPasses.cpp
View File

@ -313,7 +313,7 @@ void EliminateUnreachableBlocks::runOnFunctions(BinaryContext &BC) {
ParallelUtilities::WorkFuncTy WorkFun = [&](BinaryFunction &BF) {
runOnFunction(BF);
};
ParallelUtilities::PredicateTy SkipFunc = [&](const BinaryFunction &BF) {
return !shouldOptimize(BF);
};

2
bolt/src/Passes/DataflowAnalysis.h
View File

@ -333,7 +333,7 @@ public:
/// end.
void run() {
derived().preflight();
// Initialize state for all points of the function
for (auto &BB : Func) {
auto &St = getOrCreateStateAt(BB);

2
bolt/src/Passes/IndirectCallPromotion.cpp
View File

@ -346,7 +346,7 @@ IndirectCallPromotion::getCallTargets(
// indices and high mispredicts
std::stable_sort(Targets.begin(), Targets.end(),
[](const Callsite &A, const Callsite &B) {
if (A.Branches != B.Branches)
if (A.Branches != B.Branches)
return A.Branches > B.Branches;
else if (A.JTIndices.size() != B.JTIndices.size())
return A.JTIndices.size() < B.JTIndices.size();

2
bolt/src/Passes/ReorderAlgorithm.cpp
View File

@ -628,7 +628,7 @@ void OptimizeCacheReorderAlgorithm::reorderBasicBlocks(
const BinaryFunction &BF, BasicBlockOrder &Order) const {
if (BF.layout_empty())
return;
// Cluster basic blocks.
CAlgo->clusterBasicBlocks(BF);
std::vector<ClusterAlgorithm::ClusterTy> &Clusters = CAlgo->Clusters;

2
bolt/src/Passes/ShrinkWrapping.h
View File

@ -111,7 +111,7 @@ public:
static StringRef getSaveTagName() {
return StringRef("CSA-SavedReg");
}
static StringRef getRestoreTagName() {
return StringRef("CSA-RestoredReg");
}

4
bolt/src/Passes/StackPointerTracking.h
View File

@ -181,14 +181,14 @@ protected:
StringRef getAnnotationName() const {
return StringRef("StackPointerTracking");
}
public:
StackPointerTrackingBase(const BinaryContext &BC, BinaryFunction &BF,
MCPlusBuilder::AllocatorIdTy AllocatorId = 0)
: DataflowAnalysis<Derived, std::pair<int, int>>(BC, BF, AllocatorId) {}
virtual ~StackPointerTrackingBase() {}
bool HasFramePointer{false};
static constexpr int SUPERPOSITION = std::numeric_limits<int>::max();

2
bolt/src/RewriteInstance.h
View File

@ -296,7 +296,7 @@ public:
using SectionPatchersType =
std::map<std::string, std::unique_ptr<BinaryPatcher>>;
private:
/// Get the contents of the LSDA section for this binary.
ArrayRef<uint8_t> getLSDAData();

2
bolt/src/llvm-bolt.cpp
View File

@ -104,7 +104,7 @@ PerfDataA("p",
cl::desc("Alias for -perfdata"),
cl::aliasopt(PerfData),
cl::cat(AggregatorCategory));
} // namespace opts
static StringRef ToolName;