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R600/SI: Custom lower i64 ZERO_EXTEND 

llvm-svn: 187580
This commit is contained in:
Tom Stellard 2013-08-01 15:23:26 +00:00
parent 6459a370a7
commit 98f675a994
3 changed files with 34 additions and 0 deletions
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15
llvm/lib/Target/R600/SIISelLowering.cpp
View File

@ -79,6 +79,7 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
setOperationAction(ISD::SIGN_EXTEND, MVT::i64, Custom);
setOperationAction(ISD::ZERO_EXTEND, MVT::i64, Custom);
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
@ -346,6 +347,7 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::BRCOND: return LowerBRCOND(Op, DAG);
case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, DAG);
case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
case ISD::INTRINSIC_WO_CHAIN: {
unsigned IntrinsicID =
@ -527,6 +529,19 @@ SDValue SITargetLowering::LowerSIGN_EXTEND(SDValue Op,
return DAG.getNode(ISD::BUILD_PAIR, DL, VT, Op.getOperand(0), Hi);
}
SDValue SITargetLowering::LowerZERO_EXTEND(SDValue Op,
SelectionDAG &DAG) const {
EVT VT = Op.getValueType();
SDLoc DL(Op);
if (VT != MVT::i64) {
return SDValue();
}
return DAG.getNode(ISD::BUILD_PAIR, DL, VT, Op.getOperand(0),
DAG.getConstant(0, MVT::i32));
}
//===----------------------------------------------------------------------===//
// Custom DAG optimizations
//===----------------------------------------------------------------------===//

1
llvm/lib/Target/R600/SIISelLowering.h
View File

@ -25,6 +25,7 @@ class SITargetLowering : public AMDGPUTargetLowering {
SDValue Chain, unsigned Offset) const;
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
bool foldImm(SDValue &Operand, int32_t &Immediate,

18
llvm/test/CodeGen/R600/zero_extend.ll Normal file
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@ -0,0 +1,18 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
; R600-CHECK: @test
; R600-CHECK: RAT_WRITE_CACHELESS_32_eg
; R600-CHECK: RAT_WRITE_CACHELESS_32_eg
; SI-CHECK: @test
; SI-CHECK: V_MOV_B32_e32 [[ZERO:VGPR[0-9]]], 0
; SI-CHECK: BUFFER_STORE_DWORDX2 VGPR0_[[ZERO]]
define void @test(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
entry:
%0 = mul i32 %a, %b
%1 = add i32 %0, %c
%2 = zext i32 %1 to i64
store i64 %2, i64 addrspace(1)* %out
ret void
}