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Factor out the code to scan an instruction's operands into a 

helper function.

llvm-svn: 55007
This commit is contained in:
Dan Gohman 2008-08-19 20:56:30 +00:00
parent 547ce65467
commit 98e6f1c48a
1 changed files with 36 additions and 26 deletions
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62
llvm/utils/TableGen/FastISelEmitter.cpp
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@ -56,6 +56,40 @@ struct OperandsSignature {
bool empty() const { return Operands.empty(); } bool empty() const { return Operands.empty(); }
/// initialize - Examine the given pattern and initialize the contents
/// of the Operands array accordingly. Return true if all the operands
/// are supported, false otherwise.
///
bool initialize(TreePatternNode *InstPatNode,
const CodeGenTarget &Target,
MVT::SimpleValueType VT) {
for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
TreePatternNode *Op = InstPatNode->getChild(i);
if (!Op->isLeaf())
return false;
// For now, filter out any operand with a predicate.
if (!Op->getPredicateFn().empty())
return false;
DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
if (!OpDI)
return false;
Record *OpLeafRec = OpDI->getDef();
// For now, only accept register operands.
if (!OpLeafRec->isSubClassOf("RegisterClass"))
return false;
// For now, require the register operands' register classes to all
// be the same.
const CodeGenRegisterClass *RC = &Target.getRegisterClass(OpLeafRec);
if (!RC)
return false;
// For now, all the operands must have the same type.
if (Op->getTypeNum(0) != VT)
return false;
Operands.push_back("r");
}
return true;
}
void PrintParameters(std::ostream &OS) const { void PrintParameters(std::ostream &OS) const {
for (unsigned i = 0, e = Operands.size(); i != e; ++i) { for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
if (Operands[i] == "r") { if (Operands[i] == "r") {
@ -196,30 +230,8 @@ void FastISelEmitter::run(std::ostream &OS) {
// Check all the operands. // Check all the operands.
OperandsSignature Operands; OperandsSignature Operands;
for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) { if (!Operands.initialize(InstPatNode, Target, VT))
TreePatternNode *Op = InstPatNode->getChild(i); continue;
if (!Op->isLeaf())
goto continue_label;
// For now, filter out any operand with a predicate.
if (!Op->getPredicateFn().empty())
goto continue_label;
DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
if (!OpDI)
goto continue_label;
Record *OpLeafRec = OpDI->getDef();
// For now, only accept register operands.
if (!OpLeafRec->isSubClassOf("RegisterClass"))
goto continue_label;
// For now, require the register operands' register classes to all
// be the same.
const CodeGenRegisterClass *RC = &Target.getRegisterClass(OpLeafRec);
if (!RC)
goto continue_label;
// For now, all the operands must have the same type.
if (Op->getTypeNum(0) != VT)
goto continue_label;
Operands.Operands.push_back("r");
}
// If it's not a known signature, ignore it. // If it's not a known signature, ignore it.
if (!SimplePatterns.count(Operands)) if (!SimplePatterns.count(Operands))
@ -233,8 +245,6 @@ void FastISelEmitter::run(std::ostream &OS) {
}; };
SimplePatterns[Operands][OpcodeName][VT] = Memo; SimplePatterns[Operands][OpcodeName][VT] = Memo;
} }
continue_label:;
} }
OS << "#include \"llvm/CodeGen/FastISel.h\"\n"; OS << "#include \"llvm/CodeGen/FastISel.h\"\n";