From 98e37af27231a8927bb8d8cbff9cd54a7aa165c6 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Thu, 23 Jan 2020 17:17:24 +0000
Subject: [PATCH] [X86] Add AVX512 tests for vector rotations

---
 llvm/test/CodeGen/X86/rotate_vec.ll | 61 ++++++++++++++++++++---------
 1 file changed, 42 insertions(+), 19 deletions(-)

diff --git a/llvm/test/CodeGen/X86/rotate_vec.ll b/llvm/test/CodeGen/X86/rotate_vec.ll
index ed0c4717ea80..77ee5998599b 100644
--- a/llvm/test/CodeGen/X86/rotate_vec.ll
+++ b/llvm/test/CodeGen/X86/rotate_vec.ll
@@ -1,11 +1,17 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver4 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver4 | FileCheck %s --check-prefixes=CHECK,XOP
+; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 | FileCheck %s --check-prefixes=CHECK,AVX512
 
 define <4 x i32> @rot_v4i32_splat(<4 x i32> %x) {
-; CHECK-LABEL: rot_v4i32_splat:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vprotd $31, %xmm0, %xmm0
-; CHECK-NEXT:    retq
+; XOP-LABEL: rot_v4i32_splat:
+; XOP:       # %bb.0:
+; XOP-NEXT:    vprotd $31, %xmm0, %xmm0
+; XOP-NEXT:    retq
+;
+; AVX512-LABEL: rot_v4i32_splat:
+; AVX512:       # %bb.0:
+; AVX512-NEXT:    vprold $31, %xmm0, %xmm0
+; AVX512-NEXT:    retq
   %1 = lshr <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
   %2 = shl <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
   %3 = or <4 x i32> %1, %2
@@ -13,10 +19,15 @@ define <4 x i32> @rot_v4i32_splat(<4 x i32> %x) {
 }
 
 define <4 x i32> @rot_v4i32_non_splat(<4 x i32> %x) {
-; CHECK-LABEL: rot_v4i32_non_splat:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vprotd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-NEXT:    retq
+; XOP-LABEL: rot_v4i32_non_splat:
+; XOP:       # %bb.0:
+; XOP-NEXT:    vprotd {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT:    retq
+;
+; AVX512-LABEL: rot_v4i32_non_splat:
+; AVX512:       # %bb.0:
+; AVX512-NEXT:    vprolvd {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT:    retq
   %1 = lshr <4 x i32> %x, <i32 1, i32 2, i32 3, i32 4>
   %2 = shl <4 x i32> %x, <i32 31, i32 30, i32 29, i32 28>
   %3 = or <4 x i32> %1, %2
@@ -24,11 +35,17 @@ define <4 x i32> @rot_v4i32_non_splat(<4 x i32> %x) {
 }
 
 define <4 x i32> @rot_v4i32_splat_2masks(<4 x i32> %x) {
-; CHECK-LABEL: rot_v4i32_splat_2masks:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vprotd $31, %xmm0, %xmm0
-; CHECK-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-NEXT:    retq
+; XOP-LABEL: rot_v4i32_splat_2masks:
+; XOP:       # %bb.0:
+; XOP-NEXT:    vprotd $31, %xmm0, %xmm0
+; XOP-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT:    retq
+;
+; AVX512-LABEL: rot_v4i32_splat_2masks:
+; AVX512:       # %bb.0:
+; AVX512-NEXT:    vprold $31, %xmm0, %xmm0
+; AVX512-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT:    retq
   %1 = lshr <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
   %2 = and <4 x i32> %1, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>
 
@@ -39,11 +56,17 @@ define <4 x i32> @rot_v4i32_splat_2masks(<4 x i32> %x) {
 }
 
 define <4 x i32> @rot_v4i32_non_splat_2masks(<4 x i32> %x) {
-; CHECK-LABEL: rot_v4i32_non_splat_2masks:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vprotd {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-NEXT:    retq
+; XOP-LABEL: rot_v4i32_non_splat_2masks:
+; XOP:       # %bb.0:
+; XOP-NEXT:    vprotd {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; XOP-NEXT:    retq
+;
+; AVX512-LABEL: rot_v4i32_non_splat_2masks:
+; AVX512:       # %bb.0:
+; AVX512-NEXT:    vprolvd {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT:    retq
   %1 = lshr <4 x i32> %x, <i32 1, i32 2, i32 3, i32 4>
   %2 = and <4 x i32> %1, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>