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store LR in an arbitrary stack slot add support for writing varargs functions llvm-svn: 29876
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@ -43,7 +43,7 @@ namespace {
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Data32bitsDirective = "\t.word\t";
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Data64bitsDirective = 0;
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ZeroDirective = "\t.skip\t";
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CommentString = "#";
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CommentString = "@";
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ConstantPoolSection = "\t.text\n";
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AlignmentIsInBytes = false;
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}
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@ -22,20 +22,12 @@
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namespace llvm {
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class ARMFrameInfo: public TargetFrameInfo {
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std::pair<unsigned, int> LR[1];
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public:
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ARMFrameInfo()
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: TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) {
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LR[0].first = ARM::R14;
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LR[0].second = -4;
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}
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const std::pair<unsigned, int> *
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getCalleeSaveSpillSlots(unsigned &NumEntries) const {
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NumEntries = 1;
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return &LR[0];
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}
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};
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} // End llvm namespace
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@ -32,6 +32,7 @@ using namespace llvm;
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namespace {
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class ARMTargetLowering : public TargetLowering {
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int VarArgsFrameIndex; // FrameIndex for start of varargs area.
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public:
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ARMTargetLowering(TargetMachine &TM);
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virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
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@ -55,6 +56,9 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
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setOperationAction(ISD::BR_CC, MVT::i32, Custom);
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setOperationAction(ISD::VASTART, MVT::Other, Custom);
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setOperationAction(ISD::VAEND, MVT::Other, Expand);
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setSchedulingPreference(SchedulingForRegPressure);
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computeRegisterProperties();
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}
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@ -238,6 +242,7 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
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}
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static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
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unsigned *vRegs,
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unsigned ArgNo) {
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MachineFunction &MF = DAG.getMachineFunction();
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MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
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@ -253,6 +258,7 @@ static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
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if(ArgNo < num_regs) {
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unsigned VReg = RegMap->createVirtualRegister(&ARM::IntRegsRegClass);
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MF.addLiveIn(REGS[ArgNo], VReg);
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vRegs[ArgNo] = VReg;
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return DAG.getCopyFromReg(Root, VReg, MVT::i32);
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} else {
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// If the argument is actually used, emit a load from the right stack
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@ -291,18 +297,65 @@ static SDOperand LowerGlobalAddress(SDOperand Op,
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DAG.getSrcValue(NULL));
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}
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static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
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static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
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unsigned VarArgsFrameIndex) {
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// vastart just stores the address of the VarArgsFrameIndex slot into the
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// memory location argument.
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MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
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SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
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return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR,
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Op.getOperand(1), Op.getOperand(2));
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}
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static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
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int &VarArgsFrameIndex) {
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std::vector<SDOperand> ArgValues;
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SDOperand Root = Op.getOperand(0);
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unsigned VRegs[4];
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for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
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SDOperand ArgVal = LowerFORMAL_ARGUMENT(Op, DAG, ArgNo);
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unsigned NumArgs = Op.Val->getNumValues()-1;
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for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo) {
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SDOperand ArgVal = LowerFORMAL_ARGUMENT(Op, DAG, VRegs, ArgNo);
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ArgValues.push_back(ArgVal);
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}
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bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
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assert(!isVarArg);
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if (isVarArg) {
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MachineFunction &MF = DAG.getMachineFunction();
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SSARegMap *RegMap = MF.getSSARegMap();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(MVT::i32)/8,
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-16 + NumArgs * 4);
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static const unsigned REGS[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3
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};
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// If this function is vararg, store r0-r3 to their spots on the stack
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// so that they may be loaded by deferencing the result of va_next.
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SmallVector<SDOperand, 4> MemOps;
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for (unsigned ArgNo = 0; ArgNo < 4; ++ArgNo) {
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int ArgOffset = - (4 - ArgNo) * 4;
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int FI = MFI->CreateFixedObject(MVT::getSizeInBits(MVT::i32)/8,
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ArgOffset);
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SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
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unsigned VReg;
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if (ArgNo < NumArgs)
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VReg = VRegs[ArgNo];
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else
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VReg = RegMap->createVirtualRegister(&ARM::IntRegsRegClass);
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if (ArgNo >= NumArgs)
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MF.addLiveIn(REGS[ArgNo], VReg);
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SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
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SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
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Val, FIN, DAG.getSrcValue(NULL));
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MemOps.push_back(Store);
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}
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Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
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}
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ArgValues.push_back(Root);
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@ -346,7 +399,7 @@ SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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case ISD::GlobalAddress:
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return LowerGlobalAddress(Op, DAG);
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case ISD::FORMAL_ARGUMENTS:
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return LowerFORMAL_ARGUMENTS(Op, DAG);
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return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex);
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case ISD::CALL:
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return LowerCALL(Op, DAG);
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case ISD::RET:
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@ -355,6 +408,8 @@ SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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return LowerSELECT_CC(Op, DAG);
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case ISD::BR_CC:
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return LowerBR_CC(Op, DAG);
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case ISD::VASTART:
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return LowerVASTART(Op, DAG, VarArgsFrameIndex);
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}
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}
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