From 98cfa1044fdcaaa53625c16bb9a246e0b15f7653 Mon Sep 17 00:00:00 2001 From: Chad Rosier Date: Fri, 31 Aug 2012 00:03:31 +0000 Subject: [PATCH] With the fix in r162954/162955 every cvt function returns true. Thus, have the ConvertToMCInst() return void, rather then a bool. Update all the cvt functions as well. llvm-svn: 162961 --- .../lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 106 +++++++----------- llvm/utils/TableGen/AsmMatcherEmitter.cpp | 24 ++-- 2 files changed, 53 insertions(+), 77 deletions(-) diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index c4341bb9ba71..cc2057d20ccb 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -181,47 +181,47 @@ class ARMAsmParser : public MCTargetAsmParser { OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index); // Asm Match Converter Methods - bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode, + void cvtT2LdrdPre(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); - bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode, + void cvtT2StrdPre(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); - bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, + void cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); - bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, + void cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); - bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, + void cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); - bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, + void cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); - bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, + void cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); - bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, + void cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); - bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, + void cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); - bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, + void cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); - bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, + void cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); - bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, + void cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); - bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, + void cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); - bool cvtLdrdPre(MCInst &Inst, unsigned Opcode, + void cvtLdrdPre(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); - bool cvtStrdPre(MCInst &Inst, unsigned Opcode, + void cvtStrdPre(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); - bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, + void cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); - bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode, + void cvtThumbMultiply(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); - bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode, + void cvtVLDwbFixed(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); - bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode, + void cvtVLDwbRegister(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); - bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode, + void cvtVSTwbFixed(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); - bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode, + void cvtVSTwbRegister(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &); bool validateInstruction(MCInst &Inst, @@ -3880,7 +3880,7 @@ parseAM3Offset(SmallVectorImpl &Operands) { /// cvtT2LdrdPre - Convert parsed operands to MCInst. /// Needed here because the Asm Gen Matcher can't handle properly tied operands /// when they refer multiple MIOperands inside a single one. -bool ARMAsmParser:: +void ARMAsmParser:: cvtT2LdrdPre(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &Operands) { // Rt, Rt2 @@ -3892,13 +3892,12 @@ cvtT2LdrdPre(MCInst &Inst, unsigned Opcode, ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); // pred ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); - return true; } /// cvtT2StrdPre - Convert parsed operands to MCInst. /// Needed here because the Asm Gen Matcher can't handle properly tied operands /// when they refer multiple MIOperands inside a single one. -bool ARMAsmParser:: +void ARMAsmParser:: cvtT2StrdPre(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &Operands) { // Create a writeback register dummy placeholder. @@ -3910,13 +3909,12 @@ cvtT2StrdPre(MCInst &Inst, unsigned Opcode, ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); // pred ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); - return true; } /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. /// Needed here because the Asm Gen Matcher can't handle properly tied operands /// when they refer multiple MIOperands inside a single one. -bool ARMAsmParser:: +void ARMAsmParser:: cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &Operands) { ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); @@ -3926,13 +3924,12 @@ cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); - return true; } /// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. /// Needed here because the Asm Gen Matcher can't handle properly tied operands /// when they refer multiple MIOperands inside a single one. -bool ARMAsmParser:: +void ARMAsmParser:: cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &Operands) { // Create a writeback register dummy placeholder. @@ -3940,13 +3937,12 @@ cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); - return true; } /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst. /// Needed here because the Asm Gen Matcher can't handle properly tied operands /// when they refer multiple MIOperands inside a single one. -bool ARMAsmParser:: +void ARMAsmParser:: cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &Operands) { ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); @@ -3956,13 +3952,12 @@ cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); - return true; } /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. /// Needed here because the Asm Gen Matcher can't handle properly tied operands /// when they refer multiple MIOperands inside a single one. -bool ARMAsmParser:: +void ARMAsmParser:: cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &Operands) { ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); @@ -3972,14 +3967,13 @@ cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); - return true; } /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. /// Needed here because the Asm Gen Matcher can't handle properly tied operands /// when they refer multiple MIOperands inside a single one. -bool ARMAsmParser:: +void ARMAsmParser:: cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &Operands) { // Create a writeback register dummy placeholder. @@ -3987,13 +3981,12 @@ cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); - return true; } /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst. /// Needed here because the Asm Gen Matcher can't handle properly tied operands /// when they refer multiple MIOperands inside a single one. -bool ARMAsmParser:: +void ARMAsmParser:: cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &Operands) { // Create a writeback register dummy placeholder. @@ -4001,13 +3994,12 @@ cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); - return true; } /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst. /// Needed here because the Asm Gen Matcher can't handle properly tied operands /// when they refer multiple MIOperands inside a single one. -bool ARMAsmParser:: +void ARMAsmParser:: cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &Operands) { // Create a writeback register dummy placeholder. @@ -4015,13 +4007,12 @@ cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); - return true; } /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst. /// Needed here because the Asm Gen Matcher can't handle properly tied operands /// when they refer multiple MIOperands inside a single one. -bool ARMAsmParser:: +void ARMAsmParser:: cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &Operands) { // Rt @@ -4034,13 +4025,12 @@ cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); // pred ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); - return true; } /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst. /// Needed here because the Asm Gen Matcher can't handle properly tied operands /// when they refer multiple MIOperands inside a single one. -bool ARMAsmParser:: +void ARMAsmParser:: cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &Operands) { // Rt @@ -4053,13 +4043,12 @@ cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); // pred ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); - return true; } /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst. /// Needed here because the Asm Gen Matcher can't handle properly tied operands /// when they refer multiple MIOperands inside a single one. -bool ARMAsmParser:: +void ARMAsmParser:: cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &Operands) { // Create a writeback register dummy placeholder. @@ -4072,13 +4061,12 @@ cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); // pred ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); - return true; } /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst. /// Needed here because the Asm Gen Matcher can't handle properly tied operands /// when they refer multiple MIOperands inside a single one. -bool ARMAsmParser:: +void ARMAsmParser:: cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &Operands) { // Create a writeback register dummy placeholder. @@ -4091,13 +4079,12 @@ cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); // pred ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); - return true; } /// cvtLdrdPre - Convert parsed operands to MCInst. /// Needed here because the Asm Gen Matcher can't handle properly tied operands /// when they refer multiple MIOperands inside a single one. -bool ARMAsmParser:: +void ARMAsmParser:: cvtLdrdPre(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &Operands) { // Rt, Rt2 @@ -4109,13 +4096,12 @@ cvtLdrdPre(MCInst &Inst, unsigned Opcode, ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); // pred ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); - return true; } /// cvtStrdPre - Convert parsed operands to MCInst. /// Needed here because the Asm Gen Matcher can't handle properly tied operands /// when they refer multiple MIOperands inside a single one. -bool ARMAsmParser:: +void ARMAsmParser:: cvtStrdPre(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &Operands) { // Create a writeback register dummy placeholder. @@ -4127,13 +4113,12 @@ cvtStrdPre(MCInst &Inst, unsigned Opcode, ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); // pred ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); - return true; } /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst. /// Needed here because the Asm Gen Matcher can't handle properly tied operands /// when they refer multiple MIOperands inside a single one. -bool ARMAsmParser:: +void ARMAsmParser:: cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &Operands) { ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); @@ -4141,13 +4126,12 @@ cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, Inst.addOperand(MCOperand::CreateImm(0)); ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); - return true; } /// cvtThumbMultiply - Convert parsed operands to MCInst. /// Needed here because the Asm Gen Matcher can't handle properly tied operands /// when they refer multiple MIOperands inside a single one. -bool ARMAsmParser:: +void ARMAsmParser:: cvtThumbMultiply(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &Operands) { ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); @@ -4162,11 +4146,9 @@ cvtThumbMultiply(MCInst &Inst, unsigned Opcode, ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1); Inst.addOperand(Inst.getOperand(0)); ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2); - - return true; } -bool ARMAsmParser:: +void ARMAsmParser:: cvtVLDwbFixed(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &Operands) { // Vd @@ -4177,10 +4159,9 @@ cvtVLDwbFixed(MCInst &Inst, unsigned Opcode, ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); // pred ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); - return true; } -bool ARMAsmParser:: +void ARMAsmParser:: cvtVLDwbRegister(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &Operands) { // Vd @@ -4193,10 +4174,9 @@ cvtVLDwbRegister(MCInst &Inst, unsigned Opcode, ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); // pred ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); - return true; } -bool ARMAsmParser:: +void ARMAsmParser:: cvtVSTwbFixed(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &Operands) { // Create a writeback register dummy placeholder. @@ -4207,10 +4187,9 @@ cvtVSTwbFixed(MCInst &Inst, unsigned Opcode, ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); // pred ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); - return true; } -bool ARMAsmParser:: +void ARMAsmParser:: cvtVSTwbRegister(MCInst &Inst, unsigned Opcode, const SmallVectorImpl &Operands) { // Create a writeback register dummy placeholder. @@ -4223,7 +4202,6 @@ cvtVSTwbRegister(MCInst &Inst, unsigned Opcode, ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); // pred ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); - return true; } /// Parse an ARM memory expression, return false if successful else return true diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp index 861169e97974..8debc8e32ab9 100644 --- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp +++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp @@ -1678,12 +1678,12 @@ static void emitConvertToMCInst(CodeGenTarget &Target, StringRef ClassName, std::string ConvertFnBody; raw_string_ostream CvtOS(ConvertFnBody); // Start the unified conversion function. - CvtOS << "bool " << Target.getName() << ClassName << "::\n" + CvtOS << "void " << Target.getName() << ClassName << "::\n" << "ConvertToMCInst(unsigned Kind, MCInst &Inst, " << "unsigned Opcode,\n" << " const SmallVectorImpl &Operands) {\n" - << " if (Kind >= CVT_NUM_SIGNATURES) return false;\n" + << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n" << " uint8_t *Converter = ConversionTable[Kind];\n" << " Inst.setOpcode(Opcode);\n" << " for (uint8_t *p = Converter; *p; p+= 2) {\n" @@ -1700,11 +1700,11 @@ static void emitConvertToMCInst(CodeGenTarget &Target, StringRef ClassName, std::string OperandFnBody; raw_string_ostream OpOS(OperandFnBody); // Start the operand number lookup function. - OpOS << "bool " << Target.getName() << ClassName << "::\n" + OpOS << "void " << Target.getName() << ClassName << "::\n" << "GetMCInstOperandNum(unsigned Kind, MCInst &Inst,\n" << " const SmallVectorImpl &Operands," << "\n unsigned OperandNum, unsigned &MCOperandNum) {\n" - << " if (Kind >= CVT_NUM_SIGNATURES) return false;\n" + << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n" << " MCOperandNum = 0;\n" << " uint8_t *Converter = ConversionTable[Kind];\n" << " for (uint8_t *p = Converter; *p; p+= 2) {\n" @@ -1751,8 +1751,8 @@ static void emitConvertToMCInst(CodeGenTarget &Target, StringRef ClassName, // Add the handler to the conversion driver function. CvtOS << " case CVT_" << AsmMatchConverter << ":\n" - << " return " << AsmMatchConverter - << "(Inst, Opcode, Operands);\n"; + << " " << AsmMatchConverter << "(Inst, Opcode, Operands);\n" + << " break;\n"; // FIXME: Handle the operand number lookup for custom match functions. continue; @@ -1899,10 +1899,10 @@ static void emitConvertToMCInst(CodeGenTarget &Target, StringRef ClassName, } // Finish up the converter driver function. - CvtOS << " }\n }\n return true;\n}\n\n"; + CvtOS << " }\n }\n return;\n}\n\n"; // Finish up the operand number lookup function. - OpOS << " }\n }\n return true;\n}\n\n"; + OpOS << " }\n }\n return;\n}\n\n"; OS << "namespace {\n"; @@ -2576,11 +2576,11 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { OS << " // This should be included into the middle of the declaration of\n"; OS << " // your subclasses implementation of MCTargetAsmParser.\n"; OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const;\n"; - OS << " bool ConvertToMCInst(unsigned Kind, MCInst &Inst, " + OS << " void ConvertToMCInst(unsigned Kind, MCInst &Inst, " << "unsigned Opcode,\n" << " const SmallVectorImpl " << "&Operands);\n"; - OS << " bool GetMCInstOperandNum(unsigned Kind, MCInst &Inst,\n" + OS << " void GetMCInstOperandNum(unsigned Kind, MCInst &Inst,\n" << " const SmallVectorImpl " << "&Operands,\n unsigned OperandNum, unsigned " << "&MCOperandNum);\n"; @@ -2864,9 +2864,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { OS << "\n"; OS << " // We have selected a definite instruction, convert the parsed\n" << " // operands into the appropriate MCInst.\n"; - OS << " if (!ConvertToMCInst(it->ConvertFn, Inst,\n" - << " it->Opcode, Operands))\n"; - OS << " return Match_ConversionFail;\n"; + OS << " ConvertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n"; OS << "\n"; // Verify the instruction with the target-specific match predicate function.