forked from OSchip/llvm-project
[RISCV][NFC] Remove floating point operations from test/CodeGen/RISCV/vararg.ll
This minimises differences in output when compiling with hardware floating point support, which will be done in a future patch (to demonstrate the same vararg calling convention is used). llvm-svn: 357339
This commit is contained in:
Alex Bradbury
parent
ff852744c2
commit
98b8ecde64
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@ -214,7 +214,7 @@ define void @va1_caller() nounwind {
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; Ensure that 2x xlen size+alignment varargs are accessed via an "aligned"
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; register pair (where the first register is even-numbered).
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define double @va2(i8 *%fmt, ...) nounwind {
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define i64 @va2(i8 *%fmt, ...) nounwind {
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; RV32I-FPELIM-LABEL: va2:
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; RV32I-FPELIM: # %bb.0:
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; RV32I-FPELIM-NEXT: addi sp, sp, -48
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@ -271,11 +271,12 @@ define double @va2(i8 *%fmt, ...) nounwind {
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store i8* %argp.next, i8** %va, align 4
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%5 = inttoptr i32 %4 to double*
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%6 = load double, double* %5, align 8
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%7 = bitcast double %6 to i64
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call void @llvm.va_end(i8* %1)
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ret double %6
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ret i64 %7
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}
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define double @va2_va_arg(i8 *%fmt, ...) nounwind {
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define i64 @va2_va_arg(i8 *%fmt, ...) nounwind {
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; RV32I-FPELIM-LABEL: va2_va_arg:
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; RV32I-FPELIM: # %bb.0:
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; RV32I-FPELIM-NEXT: addi sp, sp, -48
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@ -327,7 +328,8 @@ define double @va2_va_arg(i8 *%fmt, ...) nounwind {
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call void @llvm.va_start(i8* %1)
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%2 = va_arg i8** %va, double
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call void @llvm.va_end(i8* %1)
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ret double %2
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%3 = bitcast double %2 to i64
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ret i64 %3
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}
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define void @va2_caller() nounwind {
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@ -355,35 +357,33 @@ define void @va2_caller() nounwind {
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; RV32I-WITHFP-NEXT: lw ra, 12(sp)
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; RV32I-WITHFP-NEXT: addi sp, sp, 16
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; RV32I-WITHFP-NEXT: ret
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%1 = call double (i8*, ...) @va2(i8* undef, double 1.000000e+00)
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%1 = call i64 (i8*, ...) @va2(i8* undef, double 1.000000e+00)
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ret void
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}
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; Ensure a named double argument is passed in a1 and a2, while the vararg
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; double is passed in a4 and a5 (rather than a3 and a4)
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; On RV32, Ensure a named 2*xlen argument is passed in a1 and a2, while the
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; vararg double is passed in a4 and a5 (rather than a3 and a4)
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define double @va3(i32 %a, double %b, ...) nounwind {
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define i64 @va3(i32 %a, i64 %b, ...) nounwind {
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; RV32I-FPELIM-LABEL: va3:
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; RV32I-FPELIM: # %bb.0:
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; RV32I-FPELIM-NEXT: addi sp, sp, -32
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; RV32I-FPELIM-NEXT: sw ra, 4(sp)
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; RV32I-FPELIM-NEXT: mv t0, a2
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; RV32I-FPELIM-NEXT: mv a0, a1
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; RV32I-FPELIM-NEXT: sw a7, 28(sp)
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; RV32I-FPELIM-NEXT: sw a6, 24(sp)
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; RV32I-FPELIM-NEXT: sw a5, 20(sp)
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; RV32I-FPELIM-NEXT: sw a4, 16(sp)
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; RV32I-FPELIM-NEXT: sw a3, 12(sp)
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; RV32I-FPELIM-NEXT: addi a1, sp, 27
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; RV32I-FPELIM-NEXT: sw a1, 0(sp)
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; RV32I-FPELIM-NEXT: addi a1, sp, 19
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; RV32I-FPELIM-NEXT: andi a1, a1, -8
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; RV32I-FPELIM-NEXT: lw a2, 0(a1)
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; RV32I-FPELIM-NEXT: ori a1, a1, 4
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; RV32I-FPELIM-NEXT: lw a3, 0(a1)
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; RV32I-FPELIM-NEXT: mv a1, t0
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; RV32I-FPELIM-NEXT: call __adddf3
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; RV32I-FPELIM-NEXT: lw ra, 4(sp)
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; RV32I-FPELIM-NEXT: addi a0, sp, 27
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; RV32I-FPELIM-NEXT: sw a0, 4(sp)
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; RV32I-FPELIM-NEXT: addi a0, sp, 19
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; RV32I-FPELIM-NEXT: andi a0, a0, -8
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; RV32I-FPELIM-NEXT: ori a3, a0, 4
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; RV32I-FPELIM-NEXT: lw a3, 0(a3)
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; RV32I-FPELIM-NEXT: add a2, a2, a3
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; RV32I-FPELIM-NEXT: lw a0, 0(a0)
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; RV32I-FPELIM-NEXT: add a0, a1, a0
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; RV32I-FPELIM-NEXT: sltu a1, a0, a1
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; RV32I-FPELIM-NEXT: add a1, a2, a1
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; RV32I-FPELIM-NEXT: addi sp, sp, 32
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; RV32I-FPELIM-NEXT: ret
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;
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@ -393,22 +393,22 @@ define double @va3(i32 %a, double %b, ...) nounwind {
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; RV32I-WITHFP-NEXT: sw ra, 20(sp)
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; RV32I-WITHFP-NEXT: sw s0, 16(sp)
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; RV32I-WITHFP-NEXT: addi s0, sp, 24
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; RV32I-WITHFP-NEXT: mv t0, a2
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; RV32I-WITHFP-NEXT: mv a0, a1
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; RV32I-WITHFP-NEXT: sw a7, 20(s0)
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; RV32I-WITHFP-NEXT: sw a6, 16(s0)
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; RV32I-WITHFP-NEXT: sw a5, 12(s0)
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; RV32I-WITHFP-NEXT: sw a4, 8(s0)
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; RV32I-WITHFP-NEXT: sw a3, 4(s0)
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; RV32I-WITHFP-NEXT: addi a1, s0, 19
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; RV32I-WITHFP-NEXT: sw a1, -12(s0)
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; RV32I-WITHFP-NEXT: addi a1, s0, 11
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; RV32I-WITHFP-NEXT: andi a1, a1, -8
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; RV32I-WITHFP-NEXT: lw a2, 0(a1)
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; RV32I-WITHFP-NEXT: ori a1, a1, 4
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; RV32I-WITHFP-NEXT: lw a3, 0(a1)
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; RV32I-WITHFP-NEXT: mv a1, t0
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; RV32I-WITHFP-NEXT: call __adddf3
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; RV32I-WITHFP-NEXT: addi a0, s0, 19
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; RV32I-WITHFP-NEXT: sw a0, -12(s0)
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; RV32I-WITHFP-NEXT: addi a0, s0, 11
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; RV32I-WITHFP-NEXT: andi a0, a0, -8
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; RV32I-WITHFP-NEXT: ori a3, a0, 4
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; RV32I-WITHFP-NEXT: lw a3, 0(a3)
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; RV32I-WITHFP-NEXT: add a2, a2, a3
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; RV32I-WITHFP-NEXT: lw a0, 0(a0)
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; RV32I-WITHFP-NEXT: add a0, a1, a0
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; RV32I-WITHFP-NEXT: sltu a1, a0, a1
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; RV32I-WITHFP-NEXT: add a1, a2, a1
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; RV32I-WITHFP-NEXT: lw s0, 16(sp)
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; RV32I-WITHFP-NEXT: lw ra, 20(sp)
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; RV32I-WITHFP-NEXT: addi sp, sp, 48
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@ -426,33 +426,32 @@ define double @va3(i32 %a, double %b, ...) nounwind {
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%5 = inttoptr i32 %4 to double*
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%6 = load double, double* %5, align 8
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call void @llvm.va_end(i8* %1)
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%7 = fadd double %b, %6
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ret double %7
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%7 = bitcast double %6 to i64
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%8 = add i64 %b, %7
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ret i64 %8
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}
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define double @va3_va_arg(i32 %a, double %b, ...) nounwind {
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define i64 @va3_va_arg(i32 %a, i64 %b, ...) nounwind {
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; RV32I-FPELIM-LABEL: va3_va_arg:
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; RV32I-FPELIM: # %bb.0:
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; RV32I-FPELIM-NEXT: addi sp, sp, -32
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; RV32I-FPELIM-NEXT: sw ra, 4(sp)
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; RV32I-FPELIM-NEXT: mv t0, a2
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; RV32I-FPELIM-NEXT: mv a0, a1
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; RV32I-FPELIM-NEXT: sw a7, 28(sp)
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; RV32I-FPELIM-NEXT: sw a6, 24(sp)
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; RV32I-FPELIM-NEXT: sw a5, 20(sp)
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; RV32I-FPELIM-NEXT: sw a4, 16(sp)
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; RV32I-FPELIM-NEXT: sw a3, 12(sp)
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; RV32I-FPELIM-NEXT: addi a1, sp, 19
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; RV32I-FPELIM-NEXT: andi a1, a1, -8
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; RV32I-FPELIM-NEXT: ori a3, a1, 4
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; RV32I-FPELIM-NEXT: sw a3, 0(sp)
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; RV32I-FPELIM-NEXT: lw a2, 0(a1)
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; RV32I-FPELIM-NEXT: addi a1, a3, 4
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; RV32I-FPELIM-NEXT: sw a1, 0(sp)
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; RV32I-FPELIM-NEXT: addi a0, sp, 19
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; RV32I-FPELIM-NEXT: andi a0, a0, -8
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; RV32I-FPELIM-NEXT: ori a3, a0, 4
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; RV32I-FPELIM-NEXT: sw a3, 4(sp)
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; RV32I-FPELIM-NEXT: lw a0, 0(a0)
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; RV32I-FPELIM-NEXT: addi a4, a3, 4
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; RV32I-FPELIM-NEXT: sw a4, 4(sp)
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; RV32I-FPELIM-NEXT: lw a3, 0(a3)
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; RV32I-FPELIM-NEXT: mv a1, t0
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; RV32I-FPELIM-NEXT: call __adddf3
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; RV32I-FPELIM-NEXT: lw ra, 4(sp)
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; RV32I-FPELIM-NEXT: add a2, a2, a3
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; RV32I-FPELIM-NEXT: add a0, a1, a0
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; RV32I-FPELIM-NEXT: sltu a1, a0, a1
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; RV32I-FPELIM-NEXT: add a1, a2, a1
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; RV32I-FPELIM-NEXT: addi sp, sp, 32
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; RV32I-FPELIM-NEXT: ret
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;
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@ -462,23 +461,23 @@ define double @va3_va_arg(i32 %a, double %b, ...) nounwind {
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; RV32I-WITHFP-NEXT: sw ra, 20(sp)
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; RV32I-WITHFP-NEXT: sw s0, 16(sp)
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; RV32I-WITHFP-NEXT: addi s0, sp, 24
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; RV32I-WITHFP-NEXT: mv t0, a2
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; RV32I-WITHFP-NEXT: mv a0, a1
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; RV32I-WITHFP-NEXT: sw a7, 20(s0)
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; RV32I-WITHFP-NEXT: sw a6, 16(s0)
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; RV32I-WITHFP-NEXT: sw a5, 12(s0)
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; RV32I-WITHFP-NEXT: sw a4, 8(s0)
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; RV32I-WITHFP-NEXT: sw a3, 4(s0)
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; RV32I-WITHFP-NEXT: addi a1, s0, 11
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; RV32I-WITHFP-NEXT: andi a1, a1, -8
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; RV32I-WITHFP-NEXT: ori a3, a1, 4
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; RV32I-WITHFP-NEXT: addi a0, s0, 11
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; RV32I-WITHFP-NEXT: andi a0, a0, -8
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; RV32I-WITHFP-NEXT: ori a3, a0, 4
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; RV32I-WITHFP-NEXT: sw a3, -12(s0)
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; RV32I-WITHFP-NEXT: lw a2, 0(a1)
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; RV32I-WITHFP-NEXT: addi a1, a3, 4
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; RV32I-WITHFP-NEXT: sw a1, -12(s0)
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; RV32I-WITHFP-NEXT: lw a0, 0(a0)
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; RV32I-WITHFP-NEXT: addi a4, a3, 4
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; RV32I-WITHFP-NEXT: sw a4, -12(s0)
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; RV32I-WITHFP-NEXT: lw a3, 0(a3)
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; RV32I-WITHFP-NEXT: mv a1, t0
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; RV32I-WITHFP-NEXT: call __adddf3
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; RV32I-WITHFP-NEXT: add a2, a2, a3
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; RV32I-WITHFP-NEXT: add a0, a1, a0
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; RV32I-WITHFP-NEXT: sltu a1, a0, a1
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; RV32I-WITHFP-NEXT: add a1, a2, a1
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; RV32I-WITHFP-NEXT: lw s0, 16(sp)
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; RV32I-WITHFP-NEXT: lw ra, 20(sp)
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; RV32I-WITHFP-NEXT: addi sp, sp, 48
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@ -488,8 +487,9 @@ define double @va3_va_arg(i32 %a, double %b, ...) nounwind {
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call void @llvm.va_start(i8* %1)
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%2 = va_arg i8** %va, double
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call void @llvm.va_end(i8* %1)
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%3 = fadd double %b, %2
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ret double %3
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%3 = bitcast double %2 to i64
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%4 = add i64 %b, %3
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ret i64 %4
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}
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define void @va3_caller() nounwind {
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@ -498,8 +498,8 @@ define void @va3_caller() nounwind {
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; RV32I-FPELIM-NEXT: addi sp, sp, -16
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; RV32I-FPELIM-NEXT: sw ra, 12(sp)
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; RV32I-FPELIM-NEXT: addi a0, zero, 2
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; RV32I-FPELIM-NEXT: mv a1, zero
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; RV32I-FPELIM-NEXT: lui a2, 261888
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; RV32I-FPELIM-NEXT: addi a1, zero, 1111
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; RV32I-FPELIM-NEXT: mv a2, zero
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; RV32I-FPELIM-NEXT: mv a4, zero
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; RV32I-FPELIM-NEXT: lui a5, 262144
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; RV32I-FPELIM-NEXT: call va3
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@ -514,8 +514,8 @@ define void @va3_caller() nounwind {
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; RV32I-WITHFP-NEXT: sw s0, 8(sp)
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; RV32I-WITHFP-NEXT: addi s0, sp, 16
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; RV32I-WITHFP-NEXT: addi a0, zero, 2
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; RV32I-WITHFP-NEXT: mv a1, zero
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; RV32I-WITHFP-NEXT: lui a2, 261888
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; RV32I-WITHFP-NEXT: addi a1, zero, 1111
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; RV32I-WITHFP-NEXT: mv a2, zero
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; RV32I-WITHFP-NEXT: mv a4, zero
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; RV32I-WITHFP-NEXT: lui a5, 262144
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; RV32I-WITHFP-NEXT: call va3
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@ -523,7 +523,7 @@ define void @va3_caller() nounwind {
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; RV32I-WITHFP-NEXT: lw ra, 12(sp)
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; RV32I-WITHFP-NEXT: addi sp, sp, 16
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; RV32I-WITHFP-NEXT: ret
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%1 = call double (i32, double, ...) @va3(i32 2, double 1.000000e+00, double 2.000000e+00)
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%1 = call i64 (i32, i64, ...) @va3(i32 2, i64 1111, double 2.000000e+00)
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ret void
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}
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