forked from OSchip/llvm-project
[test] Add a lit test fshl-splat-undef.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mcpu=cannonlake | FileCheck %s
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; Check the correctness of following test.
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; For this case:
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; In 32-bits targets the <i64 12, ...> will convert to <i32 12, i32 0, ...> in
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; type legalization and turn to <i32 12, i32 undef, ...> in combining due to it
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; only use the low i32 bits.
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; But the fshl is <8 x i64> fshl, the <i32 12, i32 undef, ...> will bitcast to
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; <i64 Element, ...> back. Some like:
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; ==============================================================================
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; // t1: v16i32 = Constant:i32<12>, undef:i32, Constant:i32<12>, undef:i32, ...
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; // t2: v8i64 = bitcast t1
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; // t5: v8i64 = fshl t3, t4, t2
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; ==============================================================================
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; We should make sure not "merging" <i32 12, i32 undef> to <i64 undef>
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; (We can not convert t2 to {i64 undef, i64 undef, ...})
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; That is not equal with the origin result)
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;
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define void @test_fshl(<8 x i64> %lo, <8 x i64> %hi, <8 x i64>* %arr) {
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; CHECK-LABEL: test_fshl:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: vpsrlq $1, %zmm0, %zmm0
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; CHECK-NEXT: vpternlogq $168, {{\.?LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm0
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; CHECK-NEXT: vmovdqa64 %zmm0, (%eax)
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retl
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entry:
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%fshl = call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %hi, <8 x i64> %lo, <8 x i64> <i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12>)
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%res = shufflevector <8 x i64> %fshl, <8 x i64> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 10, i32 11, i32 12, i32 13, i32 6, i32 7>
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store <8 x i64> %res, <8 x i64>* %arr, align 64
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ret void
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}
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; Function Attrs: nocallback nofree nosync nounwind readnone speculatable willreturn
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declare <8 x i64> @llvm.fshl.v8i64(<8 x i64>, <8 x i64>, <8 x i64>)
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