From 98797a5fc06c1e4885acf513d9254f285aeceeb8 Mon Sep 17 00:00:00 2001
From: Fangrui Song <i@maskray.me>
Date: Sat, 17 Oct 2020 20:36:21 -0700
Subject: [PATCH] [PrologEpilogInserter][test] Improve SpilledToReg test

D39386 made CalleeSavedInfo possible to spill a register to another register
(vector register for POWER9) but did not actually test live-in.
---
 .../CodeGen/PowerPC/prolog_vec_spills.mir     | 20 +++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/llvm/test/CodeGen/PowerPC/prolog_vec_spills.mir b/llvm/test/CodeGen/PowerPC/prolog_vec_spills.mir
index ddd459044cdb..9803b226b43c 100644
--- a/llvm/test/CodeGen/PowerPC/prolog_vec_spills.mir
+++ b/llvm/test/CodeGen/PowerPC/prolog_vec_spills.mir
@@ -16,6 +16,7 @@ body:             |
 
 # CHECK-LABEL: name:            test1BB
 # CHECK: body:             |
+# CHECK:      liveins: $x14, $x15, $x16, $v20
 # CHECK: $f1 = MTVSRD killed $x14
 # CHECK-NEXT: $f2 = MTVSRD killed $x15
 # CHECK-NEXT: $f3 = MTVSRD killed $x16
@@ -50,12 +51,19 @@ body:             |
   bb.3:
     BLR8 implicit undef $lr8, implicit undef $rm
 
+## The spilled-to registers have to be marked as live-in so that they will not be
+## clobbered before restored in the epilogue.
 # CHECK-LABEL: name:            test2BB
 # CHECK: body:             |
-# CHECK: $f0 = MTVSRD killed $x14
-# CHECK-NEXT: $f1 = MTVSRD killed $x15
-# CHECK-NEXT: $f2 = MTVSRD killed $x16
-# CHECK: $x16 = MFVSRD killed $f2
-# CHECK-NEXT: $x15 = MFVSRD killed $f1
-# CHECK-NEXT: $x14 = MFVSRD killed $f0
+# CHECK:        $f0 = MTVSRD killed $x14
+# CHECK-NEXT:   $f1 = MTVSRD killed $x15
+# CHECK-NEXT:   $f2 = MTVSRD killed $x16
+# CHECK:      bb.2:
+# CHECK-NEXT:   successors: %bb.3
+# CHECK-NEXT:   liveins: $f0, $f1, $f2
+# CHECK:      bb.3:
+# CHECK-NEXT:   liveins: $f0, $f1, $f2
+# CHECK:        $x16 = MFVSRD killed $f2
+# CHECK-NEXT:   $x15 = MFVSRD killed $f1
+# CHECK-NEXT:   $x14 = MFVSRD killed $f0
 ...