diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp
index 80d400b34400..2c88950f8fd6 100644
--- a/llvm/lib/Target/Mips/MipsFastISel.cpp
+++ b/llvm/lib/Target/Mips/MipsFastISel.cpp
@@ -1245,6 +1245,10 @@ bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
   const Value *Callee = CLI.Callee;
   MCSymbol *Symbol = CLI.Symbol;
 
+  // Do not handle FastCC.
+  if (CC == CallingConv::Fast)
+    return false;
+
   // Allow SelectionDAG isel to handle tail calls.
   if (IsTailCall)
     return false;
@@ -1422,6 +1426,11 @@ bool MipsFastISel::selectRet(const Instruction *I) {
 
   if (Ret->getNumOperands() > 0) {
     CallingConv::ID CC = F.getCallingConv();
+
+    // Do not handle FastCC.
+    if (CC == CallingConv::Fast)
+      return false;
+
     SmallVector<ISD::OutputArg, 4> Outs;
     GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
 
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll
new file mode 100644
index 000000000000..7a197b112a23
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
+; RUN:     -fast-isel=true -mips-fast-isel -fast-isel-verbose 2>&1 | \
+; RUN:   FileCheck %s
+
+; CHECK:      FastISel missed call:
+; CHECK-SAME: %call = call fastcc i32 @foo(i32 signext %a, i32 signext %b)
+
+define internal i32 @bar(i32 signext %a, i32 signext %b) {
+  %s = and i32 %a, %b
+  ret i32 %s
+}
+
+define i32 @foo(i32 signext %a, i32 signext %b) {
+  %call = call fastcc i32 @foo(i32 signext %a, i32 signext %b)
+  ret i32 %call
+}