forked from OSchip/llvm-project
[riscv] Add tests for vsetvli reuse across iterations of a loop
These variations are chosen to exercise both FRE and PRE cases involving loops which don't change state in the iteration and can thus perform vsetvli in the preheader of the loop only. At the moment, these are essentially all TODOs.
This commit is contained in:
Philip Reames
parent
d9c1d3cbcb
commit
9873623425
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@ -633,6 +633,184 @@ for.end: ; preds = %for.body, %entry
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ret void
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}
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; A single vector store in the loop with VL controlled by VLMAX
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define void @vector_init_vlmax(i64 %N, double* %c) {
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; CHECK-LABEL: vector_init_vlmax:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, mu
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; CHECK-NEXT: blez a0, .LBB12_3
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; CHECK-NEXT: # %bb.1: # %for.body.preheader
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; CHECK-NEXT: li a3, 0
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; CHECK-NEXT: slli a4, a2, 3
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; CHECK-NEXT: vmv.v.i v8, 0
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; CHECK-NEXT: .LBB12_2: # %for.body
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
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; CHECK-NEXT: vse64.v v8, (a1)
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; CHECK-NEXT: add a3, a3, a2
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; CHECK-NEXT: add a1, a1, a4
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; CHECK-NEXT: blt a3, a0, .LBB12_2
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; CHECK-NEXT: .LBB12_3: # %for.end
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
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%cmp13 = icmp sgt i64 %N, 0
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br i1 %cmp13, label %for.body, label %for.end
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for.body: ; preds = %entry, %for.body
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%i.014 = phi i64 [ %add, %for.body ], [ 0, %entry ]
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%arrayidx2 = getelementptr inbounds double, double* %c, i64 %i.014
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%addr = bitcast double* %arrayidx2 to <vscale x 1 x double>*
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tail call void @llvm.riscv.vse.nxv1f64.i64(<vscale x 1 x double> zeroinitializer, <vscale x 1 x double>* %addr, i64 %0)
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%add = add nuw nsw i64 %i.014, %0
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%cmp = icmp slt i64 %add, %N
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br i1 %cmp, label %for.body, label %for.end
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for.end: ; preds = %for.body, %entry
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ret void
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}
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; Same as above, but VL comes from user provided AVL value
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define void @vector_init_vsetvli_N(i64 %N, double* %c) {
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; CHECK-LABEL: vector_init_vsetvli_N:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a2, a0, e64, m1, ta, mu
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; CHECK-NEXT: blez a0, .LBB13_3
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; CHECK-NEXT: # %bb.1: # %for.body.preheader
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; CHECK-NEXT: li a3, 0
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; CHECK-NEXT: slli a4, a2, 3
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; CHECK-NEXT: vsetvli a5, zero, e64, m1, ta, mu
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; CHECK-NEXT: vmv.v.i v8, 0
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; CHECK-NEXT: .LBB13_2: # %for.body
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
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; CHECK-NEXT: vse64.v v8, (a1)
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; CHECK-NEXT: add a3, a3, a2
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; CHECK-NEXT: add a1, a1, a4
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; CHECK-NEXT: blt a3, a0, .LBB13_2
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; CHECK-NEXT: .LBB13_3: # %for.end
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.riscv.vsetvli(i64 %N, i64 3, i64 0)
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%cmp13 = icmp sgt i64 %N, 0
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br i1 %cmp13, label %for.body, label %for.end
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for.body: ; preds = %entry, %for.body
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%i.014 = phi i64 [ %add, %for.body ], [ 0, %entry ]
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%arrayidx2 = getelementptr inbounds double, double* %c, i64 %i.014
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%addr = bitcast double* %arrayidx2 to <vscale x 1 x double>*
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tail call void @llvm.riscv.vse.nxv1f64.i64(<vscale x 1 x double> zeroinitializer, <vscale x 1 x double>* %addr, i64 %0)
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%add = add nuw nsw i64 %i.014, %0
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%cmp = icmp slt i64 %add, %N
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br i1 %cmp, label %for.body, label %for.end
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for.end: ; preds = %for.body, %entry
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ret void
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}
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; Same as above, but VL is a hard coded constant (in the preheader)
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define void @vector_init_vsetvli_fv(i64 %N, double* %c) {
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; CHECK-LABEL: vector_init_vsetvli_fv:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li a2, 0
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; CHECK-NEXT: vsetivli a3, 4, e64, m1, ta, mu
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; CHECK-NEXT: slli a4, a3, 3
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; CHECK-NEXT: vsetvli a5, zero, e64, m1, ta, mu
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; CHECK-NEXT: vmv.v.i v8, 0
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; CHECK-NEXT: .LBB14_1: # %for.body
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vsetvli zero, a3, e64, m1, ta, mu
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; CHECK-NEXT: vse64.v v8, (a1)
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; CHECK-NEXT: add a2, a2, a3
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; CHECK-NEXT: add a1, a1, a4
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; CHECK-NEXT: blt a2, a0, .LBB14_1
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; CHECK-NEXT: # %bb.2: # %for.end
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.riscv.vsetvli(i64 4, i64 3, i64 0)
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%i.014 = phi i64 [ %add, %for.body ], [ 0, %entry ]
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%arrayidx2 = getelementptr inbounds double, double* %c, i64 %i.014
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%addr = bitcast double* %arrayidx2 to <vscale x 1 x double>*
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tail call void @llvm.riscv.vse.nxv1f64.i64(<vscale x 1 x double> zeroinitializer, <vscale x 1 x double>* %addr, i64 %0)
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%add = add nuw nsw i64 %i.014, %0
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%cmp = icmp slt i64 %add, %N
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br i1 %cmp, label %for.body, label %for.end
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for.end: ; preds = %for.body
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ret void
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}
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; Same as above, but result of vsetvli in preheader isn't used, and
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; constant is repeated in loop
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define void @vector_init_vsetvli_fv2(i64 %N, double* %c) {
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; CHECK-LABEL: vector_init_vsetvli_fv2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li a2, 0
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; CHECK-NEXT: vsetivli zero, 4, e64, m1, ta, mu
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; CHECK-NEXT: vsetvli a3, zero, e64, m1, ta, mu
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; CHECK-NEXT: vmv.v.i v8, 0
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; CHECK-NEXT: .LBB15_1: # %for.body
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vsetivli zero, 4, e64, m1, ta, mu
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; CHECK-NEXT: vse64.v v8, (a1)
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; CHECK-NEXT: addi a2, a2, 4
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; CHECK-NEXT: addi a1, a1, 32
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; CHECK-NEXT: blt a2, a0, .LBB15_1
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; CHECK-NEXT: # %bb.2: # %for.end
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; CHECK-NEXT: ret
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entry:
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tail call i64 @llvm.riscv.vsetvli(i64 4, i64 3, i64 0)
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%i.014 = phi i64 [ %add, %for.body ], [ 0, %entry ]
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%arrayidx2 = getelementptr inbounds double, double* %c, i64 %i.014
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%addr = bitcast double* %arrayidx2 to <vscale x 1 x double>*
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tail call void @llvm.riscv.vse.nxv1f64.i64(<vscale x 1 x double> zeroinitializer, <vscale x 1 x double>* %addr, i64 4)
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%add = add nuw nsw i64 %i.014, 4
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%cmp = icmp slt i64 %add, %N
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br i1 %cmp, label %for.body, label %for.end
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for.end: ; preds = %for.body
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ret void
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}
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; Same as above, but AVL is only specified on the store intrinsic
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; This case will require some form of hoisting or PRE
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define void @vector_init_vsetvli_fv3(i64 %N, double* %c) {
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; CHECK-LABEL: vector_init_vsetvli_fv3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li a2, 0
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; CHECK-NEXT: vsetvli a3, zero, e64, m1, ta, mu
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; CHECK-NEXT: vmv.v.i v8, 0
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; CHECK-NEXT: .LBB16_1: # %for.body
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vsetivli zero, 4, e64, m1, ta, mu
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; CHECK-NEXT: vse64.v v8, (a1)
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; CHECK-NEXT: addi a2, a2, 4
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; CHECK-NEXT: addi a1, a1, 32
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; CHECK-NEXT: blt a2, a0, .LBB16_1
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; CHECK-NEXT: # %bb.2: # %for.end
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; CHECK-NEXT: ret
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%i.014 = phi i64 [ %add, %for.body ], [ 0, %entry ]
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%arrayidx2 = getelementptr inbounds double, double* %c, i64 %i.014
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%addr = bitcast double* %arrayidx2 to <vscale x 1 x double>*
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tail call void @llvm.riscv.vse.nxv1f64.i64(<vscale x 1 x double> zeroinitializer, <vscale x 1 x double>* %addr, i64 4)
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%add = add nuw nsw i64 %i.014, 4
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%cmp = icmp slt i64 %add, %N
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br i1 %cmp, label %for.body, label %for.end
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for.end: ; preds = %for.body
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ret void
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}
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declare i64 @llvm.riscv.vsetvlimax.i64(i64, i64)
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declare <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>* nocapture, i64)
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declare <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, i64)
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