forked from OSchip/llvm-project
[MCA] Remove dependency from InstrBuilder in mca::Context. NFC
InstrBuilder is not required to construct the default pipeline. llvm-svn: 368275
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caef930699
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987331671f
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@ -20,7 +20,6 @@
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MCA/HardwareUnits/HardwareUnit.h"
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#include "llvm/MCA/InstrBuilder.h"
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#include "llvm/MCA/Pipeline.h"
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#include "llvm/MCA/SourceMgr.h"
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#include <memory>
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@ -58,6 +57,9 @@ public:
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Context(const Context &C) = delete;
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Context &operator=(const Context &C) = delete;
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const MCRegisterInfo &getMCRegisterInfo() const { return MRI; }
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const MCSubtargetInfo &getMCSubtargetInfo() const { return STI; }
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void addHardwareUnit(std::unique_ptr<HardwareUnit> H) {
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Hardware.push_back(std::move(H));
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}
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@ -65,7 +67,6 @@ public:
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/// Construct a basic pipeline for simulating an out-of-order pipeline.
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/// This pipeline consists of Fetch, Dispatch, Execute, and Retire stages.
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std::unique_ptr<Pipeline> createDefaultPipeline(const PipelineOptions &Opts,
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InstrBuilder &IB,
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SourceMgr &SrcMgr);
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};
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@ -28,8 +28,7 @@ namespace llvm {
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namespace mca {
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std::unique_ptr<Pipeline>
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Context::createDefaultPipeline(const PipelineOptions &Opts, InstrBuilder &IB,
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SourceMgr &SrcMgr) {
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Context::createDefaultPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr) {
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const MCSchedModel &SM = STI.getSchedModel();
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// Create the hardware units defining the backend.
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@ -34,9 +34,12 @@
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#include "Views/TimelineView.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCObjectFileInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MCA/Context.h"
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#include "llvm/MCA/InstrBuilder.h"
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#include "llvm/MCA/Pipeline.h"
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#include "llvm/MCA/Stages/EntryStage.h"
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#include "llvm/MCA/Stages/InstructionTables.h"
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@ -307,28 +310,6 @@ int main(int argc, char **argv) {
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// Apply overrides to llvm-mca specific options.
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processViewOptions();
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SourceMgr SrcMgr;
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// Tell SrcMgr about this buffer, which is what the parser will pick up.
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SrcMgr.AddNewSourceBuffer(std::move(*BufferPtr), SMLoc());
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std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName));
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assert(MRI && "Unable to create target register info!");
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std::unique_ptr<MCAsmInfo> MAI(TheTarget->createMCAsmInfo(*MRI, TripleName));
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assert(MAI && "Unable to create target asm info!");
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MCObjectFileInfo MOFI;
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MCContext Ctx(MAI.get(), MRI.get(), &MOFI, &SrcMgr);
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MOFI.InitMCObjectFileInfo(TheTriple, /* PIC= */ false, Ctx);
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std::unique_ptr<buffer_ostream> BOS;
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std::unique_ptr<MCInstrInfo> MCII(TheTarget->createMCInstrInfo());
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std::unique_ptr<MCInstrAnalysis> MCIA(
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TheTarget->createMCInstrAnalysis(MCII.get()));
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if (!MCPU.compare("native"))
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MCPU = llvm::sys::getHostCPUName();
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@ -356,6 +337,29 @@ int main(int argc, char **argv) {
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return 1;
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}
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std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName));
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assert(MRI && "Unable to create target register info!");
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std::unique_ptr<MCAsmInfo> MAI(TheTarget->createMCAsmInfo(*MRI, TripleName));
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assert(MAI && "Unable to create target asm info!");
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MCObjectFileInfo MOFI;
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SourceMgr SrcMgr;
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// Tell SrcMgr about this buffer, which is what the parser will pick up.
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SrcMgr.AddNewSourceBuffer(std::move(*BufferPtr), SMLoc());
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MCContext Ctx(MAI.get(), MRI.get(), &MOFI, &SrcMgr);
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MOFI.InitMCObjectFileInfo(TheTriple, /* PIC= */ false, Ctx);
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std::unique_ptr<buffer_ostream> BOS;
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std::unique_ptr<MCInstrInfo> MCII(TheTarget->createMCInstrInfo());
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std::unique_ptr<MCInstrAnalysis> MCIA(
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TheTarget->createMCInstrAnalysis(MCII.get()));
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// Parse the input and create CodeRegions that llvm-mca can analyze.
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mca::AsmCodeRegionGenerator CRG(*TheTarget, SrcMgr, Ctx, *MAI, *STI, *MCII);
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Expected<const mca::CodeRegions &> RegionsOrErr = CRG.parseCodeRegions();
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@ -487,7 +491,7 @@ int main(int argc, char **argv) {
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}
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// Create a basic pipeline simulating an out-of-order backend.
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auto P = MCA.createDefaultPipeline(PO, IB, S);
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auto P = MCA.createDefaultPipeline(PO, S);
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mca::PipelinePrinter Printer(*P);
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if (PrintSummaryView)
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