forked from OSchip/llvm-project
Add emulate_add_rd_sp_imm (SP plus immediate) to the g_arm_opcodes and g_thumb_opcodes tables.
Change the data type of Context.arg2 to int64_t due to possible negative values. llvm-svn: 124343
This commit is contained in:
Johnny Chen
parent
3989fb9211
commit
9864b5ec5f
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@ -30,9 +30,9 @@ public:
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struct Context
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{
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ContextType type;
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lldb::addr_t arg0;
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lldb::addr_t arg1;
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lldb::addr_t arg2;
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lldb::addr_t arg0; // Register kind.
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lldb::addr_t arg1; // Register spec.
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int64_t arg2; // Possible negative value.
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};
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union Opcode
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@ -192,6 +192,67 @@ emulate_push (EmulateInstructionARM *emulator, ARMEncoding encoding)
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return true;
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}
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// Adjust r7 or ip to point to saved value residing within the stack.
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// ADD (SP plus immediate)
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static bool
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emulate_add_rd_sp_imm (EmulateInstructionARM *emulator, ARMEncoding encoding)
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{
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#if 0
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// ARM pseudo code...
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if (ConditionPassed())
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{
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EncodingSpecificOperations();
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(result, carry, overflow) = AddWithCarry(SP, imm32, ‘0’);
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if d == 15 then
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ALUWritePC(result); // setflags is always FALSE here
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else
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R[d] = result;
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if setflags then
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APSR.N = result<31>;
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APSR.Z = IsZeroBit(result);
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APSR.C = carry;
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APSR.V = overflow;
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}
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#endif
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bool success = false;
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const uint32_t opcode = emulator->OpcodeAsUnsigned (&success);
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if (!success)
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return false;
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if (emulator->ConditionPassed())
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{
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const addr_t sp = emulator->ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success);
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if (!success)
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return false;
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uint32_t Rd; // the destination register
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uint32_t imm32;
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switch (encoding) {
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case eEncodingT1:
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Rd = 7;
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imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32)
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break;
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case eEncodingA1:
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Rd = Bits32(opcode, 15, 12);
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imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
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break;
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default:
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return false;
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}
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addr_t sp_offset = imm32;
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addr_t addr = sp + sp_offset; // a pointer to the stack area
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EmulateInstruction::Context context = { EmulateInstruction::eContextRegisterPlusOffset,
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eRegisterKindGeneric,
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LLDB_REGNUM_GENERIC_SP,
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sp_offset };
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if (!emulator->WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, addr))
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return false;
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}
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return true;
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}
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// A sub operation to adjust the SP -- allocate space for local storage.
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static bool
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emulate_sub_sp_imm (EmulateInstructionARM *emulator, ARMEncoding encoding)
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@ -423,49 +484,43 @@ emulate_vpush (EmulateInstructionARM *emulator, ARMEncoding encoding)
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static ARMOpcode g_arm_opcodes[] =
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{
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// push register(s)
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{ 0x0fff0000, 0x092d0000, ARMvAll, eEncodingA1, eSize32, emulate_push,
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"push <registers> ; <registers> contains more than one register" },
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{ 0x0fff0fff, 0x052d0004, ARMvAll, eEncodingA2, eSize32, emulate_push,
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"push <registers> ; <registers> contains one register, <Rt>" },
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{ 0x0fff0000, 0x092d0000, ARMvAll, eEncodingA1, eSize32, emulate_push, "push <registers>" },
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{ 0x0fff0fff, 0x052d0004, ARMvAll, eEncodingA2, eSize32, emulate_push, "push <register>" },
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// adjust r7 to point to a stack offset
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{ 0x0ffff000, 0x028d7000, ARMvAll, eEncodingA1, eSize32, emulate_add_rd_sp_imm, "add r7, sp, #<const>" },
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// adjust ip to point to a stack offset
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{ 0x0ffff000, 0x028dc000, ARMvAll, eEncodingA1, eSize32, emulate_add_rd_sp_imm, "add ip, sp, #<const>" },
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// adjust the stack pointer
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{ 0x0ffff000, 0x024dd000, ARMvAll, eEncodingA1, eSize32, emulate_sub_sp_imm,
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"sub sp, sp, #<const>"},
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{ 0x0ffff000, 0x024dd000, ARMvAll, eEncodingA1, eSize32, emulate_sub_sp_imm, "sub sp, sp, #<const>"},
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// if Rn == '1101' && imm12 == '000000000100' then SEE PUSH;
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{ 0x0fff0000, 0x052d0000, ARMvAll, eEncodingA1, eSize32, emulate_str_rt_sp,
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"str Rt, [sp, #-<imm12>]!" },
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{ 0x0fff0000, 0x052d0000, ARMvAll, eEncodingA1, eSize32, emulate_str_rt_sp, "str Rt, [sp, #-<imm12>]!" },
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// vector push consecutive extension register(s)
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{ 0x0fbf0f00, 0x0d2d0b00, ARMv6T2|ARMv7, eEncodingA1, eSize32, emulate_vpush,
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"vpush.64 <list>"},
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{ 0x0fbf0f00, 0x0d2d0a00, ARMv6T2|ARMv7, eEncodingA2, eSize32, emulate_vpush,
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"vpush.32 <list>"}
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{ 0x0fbf0f00, 0x0d2d0b00, ARMv6T2|ARMv7, eEncodingA1, eSize32, emulate_vpush, "vpush.64 <list>"},
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{ 0x0fbf0f00, 0x0d2d0a00, ARMv6T2|ARMv7, eEncodingA2, eSize32, emulate_vpush, "vpush.32 <list>"}
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};
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static ARMOpcode g_thumb_opcodes[] =
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{
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// push register(s)
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{ 0xfffffe00, 0x0000b400, ARMvAll, eEncodingT1, eSize16, emulate_push,
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"push <registers>" },
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{ 0xffff0000, 0xe92d0000, ARMv6T2|ARMv7, eEncodingT2, eSize32, emulate_push,
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"push.w <registers> ; <registers> contains more than one register" },
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{ 0xffff0fff, 0xf84d0d04, ARMv6T2|ARMv7, eEncodingT3, eSize32, emulate_push,
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"push.w <registers> ; <registers> contains one register, <Rt>" },
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{ 0xfffffe00, 0x0000b400, ARMvAll, eEncodingT1, eSize16, emulate_push, "push <registers>" },
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{ 0xffff0000, 0xe92d0000, ARMv6T2|ARMv7, eEncodingT2, eSize32, emulate_push, "push.w <registers>" },
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{ 0xffff0fff, 0xf84d0d04, ARMv6T2|ARMv7, eEncodingT3, eSize32, emulate_push, "push.w <register>" },
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// adjust r7 to point to a stack offset
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{ 0xffffff00, 0x000af00, ARMvAll, eEncodingT1, eSize16, emulate_add_rd_sp_imm, "add r7, sp, #<imm>" },
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// adjust the stack pointer
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{ 0xffffff80, 0x0000b080, ARMvAll, eEncodingT1, eSize16, emulate_sub_sp_imm,
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"sub{s} sp, sp, #<imm>"},
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{ 0xfbef8f00, 0xf1ad0d00, ARMv6T2|ARMv7, eEncodingT2, eSize32, emulate_sub_sp_imm,
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"sub{s}.w sp, sp, #<const>"},
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{ 0xfbff8f00, 0xf2ad0d00, ARMv6T2|ARMv7, eEncodingT3, eSize32, emulate_sub_sp_imm,
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"subw sp, sp, #<imm12>"},
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{ 0xffffff80, 0x0000b080, ARMvAll, eEncodingT1, eSize16, emulate_sub_sp_imm, "sub{s} sp, sp, #<imm>"},
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{ 0xfbef8f00, 0xf1ad0d00, ARMv6T2|ARMv7, eEncodingT2, eSize32, emulate_sub_sp_imm, "sub{s}.w sp, sp, #<const>"},
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{ 0xfbff8f00, 0xf2ad0d00, ARMv6T2|ARMv7, eEncodingT3, eSize32, emulate_sub_sp_imm, "subw sp, sp, #<imm12>"},
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// vector push consecutive extension register(s)
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{ 0xffbf0f00, 0xed2d0b00, ARMv6T2|ARMv7, eEncodingT1, eSize32, emulate_vpush,
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"vpush.64 <list>"},
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{ 0xffbf0f00, 0xed2d0a00, ARMv6T2|ARMv7, eEncodingT2, eSize32, emulate_vpush,
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"vpush.32 <list>"}
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{ 0xffbf0f00, 0xed2d0b00, ARMv6T2|ARMv7, eEncodingT1, eSize32, emulate_vpush, "vpush.64 <list>"},
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{ 0xffbf0f00, 0xed2d0a00, ARMv6T2|ARMv7, eEncodingT2, eSize32, emulate_vpush, "vpush.32 <list>"}
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};
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static const size_t k_num_arm_opcodes = sizeof(g_arm_opcodes)/sizeof(ARMOpcode);
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