[Target] Use llvm::append_range (NFC)

llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp

@@ -392,8 +392,7 @@ bool AMDGPUUnifyDivergentExitNodes::runOnFunction(Function &F) {
   // uniformly reached block with the "done" bit cleared.
   auto BlocksToUnify = std::move(ReturningBlocks);
   if (InsertExport) {
-    BlocksToUnify.insert(BlocksToUnify.end(), UniformlyReachedRetBlocks.begin(),
-                         UniformlyReachedRetBlocks.end());
+    llvm::append_range(BlocksToUnify, UniformlyReachedRetBlocks);
   }
 
   unifyReturnBlockSet(F, DTU, BlocksToUnify, InsertExport, TTI,

llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp

@@ -45,7 +45,7 @@ void R600SchedStrategy::initialize(ScheduleDAGMI *dag) {
 void R600SchedStrategy::MoveUnits(std::vector<SUnit *> &QSrc,
                                   std::vector<SUnit *> &QDst)
 {
-  QDst.insert(QDst.end(), QSrc.begin(), QSrc.end());
+  llvm::append_range(QDst, QSrc);
   QSrc.clear();
 }
 

llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp

@@ -763,8 +763,7 @@ void SIScheduleBlockCreator::colorHighLatenciesGroups() {
           // depend (order dependency) on one of the
           // instruction in the block, and are required for the
           // high latency instruction we add.
-          AdditionalElements.insert(AdditionalElements.end(),
-                                    SubGraph.begin(), SubGraph.end());
+          llvm::append_range(AdditionalElements, SubGraph);
         }
       }
       if (CompatibleGroup) {

llvm/lib/Target/BPF/BPFAdjustOpt.cpp

@@ -301,7 +301,7 @@ bool BPFAdjustOptImpl::avoidSpeculation(Instruction &I) {
   if (!isCandidate || Candidates.empty())
     return false;
 
-  PassThroughs.insert(PassThroughs.end(), Candidates.begin(), Candidates.end());
+  llvm::append_range(PassThroughs, Candidates);
   return true;
 }
 

llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp

@@ -447,7 +447,7 @@ static void nodes_for_root(GepNode *Root, NodeChildrenMap &NCM,
       Work.erase(First);
       NodeChildrenMap::iterator CF = NCM.find(N);
       if (CF != NCM.end()) {
-        Work.insert(Work.end(), CF->second.begin(), CF->second.end());
+        llvm::append_range(Work, CF->second);
         Nodes.insert(CF->second.begin(), CF->second.end());
       }
     }
@@ -1145,7 +1145,7 @@ void HexagonCommonGEP::getAllUsersForNode(GepNode *Node, ValueVect &Values,
     NodeChildrenMap::iterator CF = NCM.find(N);
     if (CF != NCM.end()) {
       NodeVect &Cs = CF->second;
-      Work.insert(Work.end(), Cs.begin(), Cs.end());
+      llvm::append_range(Work, Cs);
     }
   }
 }

llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp

@@ -585,7 +585,7 @@ auto AlignVectors::createLoadGroups(const AddrList &Group) const -> MoveList {
     if (llvm::any_of(Deps, inAddrMap))
       return false;
     Move.Main.push_back(Info.Inst);
-    Move.Deps.insert(Move.Deps.end(), Deps.begin(), Deps.end());
+    llvm::append_range(Move.Deps, Deps);
     return true;
   };
 

llvm/lib/Target/X86/X86ISelLowering.cpp

@@ -3513,8 +3513,7 @@ void VarArgsLoweringHelper::createVarArgAreaAndStoreRegisters(
           DAG.getTargetConstant(FuncInfo->getRegSaveFrameIndex(), DL, MVT::i32));
       SaveXMMOps.push_back(
           DAG.getTargetConstant(FuncInfo->getVarArgsFPOffset(), DL, MVT::i32));
-      SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
-                        LiveXMMRegs.end());
+      llvm::append_range(SaveXMMOps, LiveXMMRegs);
       MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, DL,
                                    MVT::Other, SaveXMMOps));
     }

llvm/lib/Target/X86/X86InstrInfo.cpp

@@ -6464,7 +6464,7 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
   }
   if (Load)
     BeforeOps.push_back(SDValue(Load, 0));
-  BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
+  llvm::append_range(BeforeOps, AfterOps);
   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
   switch (Opc) {
     default: break;