forked from OSchip/llvm-project
Added gdb-remote tests for Q{Save,Restore}RegisterState.
Tests for both thread suffix and no thread suffix execution. Moved some bit-flipping helper methods from TestLldbGdbServer into the base GdbRemoteTestCaseBase class. llvm-svn: 211381
This commit is contained in:
Todd Fiala
parent
eb57aa65dc
commit
9846d45d97
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@ -0,0 +1,132 @@
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import unittest2
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import gdbremote_testcase
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from lldbtest import *
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class TestGdbRemoteRegisterState(gdbremote_testcase.GdbRemoteTestCaseBase):
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"""Test QSaveRegisterState/QRestoreRegisterState support."""
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def grp_register_save_restore_works(self, with_suffix):
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# Start up the process, use thread suffix, grab main thread id.
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inferior_args = ["message:main entered", "sleep:5"]
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procs = self.prep_debug_monitor_and_inferior(inferior_args=inferior_args)
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self.add_process_info_collection_packets()
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self.add_register_info_collection_packets()
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if with_suffix:
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self.add_thread_suffix_request_packets()
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self.add_threadinfo_collection_packets()
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self.test_sequence.add_log_lines([
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# Start the inferior...
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"read packet: $c#00",
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# ... match output....
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{ "type":"output_match", "regex":r"^message:main entered\r\n$" },
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], True)
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# ... then interrupt.
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self.add_interrupt_packets()
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context = self.expect_gdbremote_sequence()
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self.assertIsNotNone(context)
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# Gather process info.
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process_info = self.parse_process_info_response(context)
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endian = process_info.get("endian")
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self.assertIsNotNone(endian)
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# Gather register info.
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reg_infos = self.parse_register_info_packets(context)
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self.assertIsNotNone(reg_infos)
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self.add_lldb_register_index(reg_infos)
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# Pull out the register infos that we think we can bit flip successfully.
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gpr_reg_infos = [reg_info for reg_info in reg_infos if self.is_bit_flippable_register(reg_info)]
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self.assertTrue(len(gpr_reg_infos) > 0)
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# Gather thread info.
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if with_suffix:
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threads = self.parse_threadinfo_packets(context)
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self.assertIsNotNone(threads)
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thread_id = threads[0]
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self.assertIsNotNone(thread_id)
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# print "Running on thread: 0x{:x}".format(thread_id)
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else:
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thread_id = None
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# Save register state.
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self.reset_test_sequence()
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self.add_QSaveRegisterState_packets(thread_id)
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context = self.expect_gdbremote_sequence()
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self.assertIsNotNone(context)
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(success, state_id) = self.parse_QSaveRegisterState_response(context)
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self.assertTrue(success)
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self.assertIsNotNone(state_id)
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# print "saved register state id: {}".format(state_id)
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# Remember initial register values.
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initial_reg_values = self.read_register_values(gpr_reg_infos, endian, thread_id=thread_id)
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# print "initial_reg_values: {}".format(initial_reg_values)
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# Flip gpr register values.
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(successful_writes, failed_writes) = self.flip_all_bits_in_each_register_value(gpr_reg_infos, endian, thread_id=thread_id)
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# print "successful writes: {}, failed writes: {}".format(successful_writes, failed_writes)
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self.assertTrue(successful_writes > 0)
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flipped_reg_values = self.read_register_values(gpr_reg_infos, endian, thread_id=thread_id)
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# print "flipped_reg_values: {}".format(flipped_reg_values)
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# Restore register values.
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self.reset_test_sequence()
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self.add_QRestoreRegisterState_packets(state_id, thread_id)
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context = self.expect_gdbremote_sequence()
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self.assertIsNotNone(context)
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# Verify registers match initial register values.
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final_reg_values = self.read_register_values(gpr_reg_infos, endian, thread_id=thread_id)
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# print "final_reg_values: {}".format(final_reg_values)
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self.assertIsNotNone(final_reg_values)
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self.assertEquals(final_reg_values, initial_reg_values)
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@debugserver_test
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@dsym_test
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def test_grp_register_save_restore_works_with_suffix_debugserver_dsym(self):
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USE_THREAD_SUFFIX = True
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self.init_debugserver_test()
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self.buildDsym()
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self.set_inferior_startup_launch()
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self.grp_register_save_restore_works(USE_THREAD_SUFFIX)
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@llgs_test
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@dwarf_test
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@unittest2.expectedFailure()
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def test_grp_register_save_restore_works_with_suffix_llgs_dwarf(self):
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USE_THREAD_SUFFIX = True
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self.init_llgs_test()
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self.buildDwarf()
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self.set_inferior_startup_launch()
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self.grp_register_save_restore_works(USE_THREAD_SUFFIX)
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@debugserver_test
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@dsym_test
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def test_grp_register_save_restore_works_no_suffix_debugserver_dsym(self):
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USE_THREAD_SUFFIX = False
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self.init_debugserver_test()
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self.buildDsym()
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self.set_inferior_startup_launch()
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self.grp_register_save_restore_works(USE_THREAD_SUFFIX)
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@llgs_test
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@dwarf_test
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@unittest2.expectedFailure()
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def test_grp_register_save_restore_works_no_suffix_llgs_dwarf(self):
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USE_THREAD_SUFFIX = False
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self.init_llgs_test()
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self.buildDwarf()
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self.set_inferior_startup_launch()
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self.grp_register_save_restore_works(USE_THREAD_SUFFIX)
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if __name__ == '__main__':
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unittest2.main()
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@ -1670,99 +1670,6 @@ class LldbGdbServerTestCase(gdbremote_testcase.GdbRemoteTestCaseBase):
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self.set_inferior_startup_launch()
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self.written_M_content_reads_back_correctly()
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def flip_all_bits_in_each_register_value(self, reg_infos, endian):
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self.assertIsNotNone(reg_infos)
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successful_writes = 0
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failed_writes = 0
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for reg_info in reg_infos:
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# Use the lldb register index added to the reg info. We're not necessarily
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# working off a full set of register infos, so an inferred register index could be wrong.
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reg_index = reg_info["lldb_register_index"]
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self.assertIsNotNone(reg_index)
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reg_byte_size = int(reg_info["bitsize"])/8
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self.assertTrue(reg_byte_size > 0)
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# Read the existing value.
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self.reset_test_sequence()
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self.test_sequence.add_log_lines(
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["read packet: $p{0:x}#00".format(reg_index),
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{ "direction":"send", "regex":r"^\$([0-9a-fA-F]+)#", "capture":{1:"p_response"} }],
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True)
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context = self.expect_gdbremote_sequence()
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self.assertIsNotNone(context)
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# Verify the response length.
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p_response = context.get("p_response")
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self.assertIsNotNone(p_response)
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initial_reg_value = lldbgdbserverutils.unpack_register_hex_unsigned(endian, p_response)
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# Flip the value by xoring with all 1s
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all_one_bits_raw = "ff" * (int(reg_info["bitsize"]) / 8)
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flipped_bits_int = initial_reg_value ^ int(all_one_bits_raw, 16)
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# print "reg (index={}, name={}): val={}, flipped bits (int={}, hex={:x})".format(reg_index, reg_info["name"], initial_reg_value, flipped_bits_int, flipped_bits_int)
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# Write the flipped value to the register.
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self.reset_test_sequence()
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self.test_sequence.add_log_lines(
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["read packet: $P{0:x}={1}#00".format(reg_index, lldbgdbserverutils.pack_register_hex(endian, flipped_bits_int, byte_size=reg_byte_size)),
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{ "direction":"send", "regex":r"^\$(OK|E[0-9a-fA-F]+)#[0-9a-fA-F]{2}", "capture":{1:"P_response"} },
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], True)
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context = self.expect_gdbremote_sequence()
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self.assertIsNotNone(context)
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# Determine if the write succeeded. There are a handful of registers that can fail, or partially fail
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# (e.g. flags, segment selectors, etc.) due to register value restrictions. Don't worry about them
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# all flipping perfectly.
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P_response = context.get("P_response")
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self.assertIsNotNone(P_response)
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if P_response == "OK":
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successful_writes += 1
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else:
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failed_writes += 1
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# print "reg (index={}, name={}) write FAILED (error: {})".format(reg_index, reg_info["name"], P_response)
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# Read back the register value, ensure it matches the flipped value.
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if P_response == "OK":
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self.reset_test_sequence()
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self.test_sequence.add_log_lines(
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["read packet: $p{0:x}#00".format(reg_index),
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{ "direction":"send", "regex":r"^\$([0-9a-fA-F]+)#", "capture":{1:"p_response"} }],
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True)
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context = self.expect_gdbremote_sequence()
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self.assertIsNotNone(context)
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verify_p_response_raw = context.get("p_response")
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self.assertIsNotNone(verify_p_response_raw)
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verify_bits = lldbgdbserverutils.unpack_register_hex_unsigned(endian, verify_p_response_raw)
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if verify_bits != flipped_bits_int:
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# Some registers, like mxcsrmask and others, will permute what's written. Adjust succeed/fail counts.
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# print "reg (index={}, name={}): read verify FAILED: wrote {:x}, verify read back {:x}".format(reg_index, reg_info["name"], flipped_bits_int, verify_bits)
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successful_writes -= 1
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failed_writes +=1
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return (successful_writes, failed_writes)
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def is_bit_flippable_register(self, reg_info):
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if not reg_info:
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return False
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if not "set" in reg_info:
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return False
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if reg_info["set"] != "General Purpose Registers":
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return False
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if ("container-regs" in reg_info) and (len(reg_info["container-regs"]) > 0):
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# Don't try to bit flip registers contained in another register.
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return False
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if re.match("^.s$", reg_info["name"]):
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# This is a 2-letter register name that ends in "s", like a segment register.
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# Don't try to bit flip these.
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return False
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# Okay, this looks fine-enough.
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return True
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def P_writes_all_gpr_registers(self):
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# Start inferior debug session, grab all register info.
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procs = self.prep_debug_monitor_and_inferior(inferior_args=["sleep:2"])
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@ -1784,7 +1691,7 @@ class LldbGdbServerTestCase(gdbremote_testcase.GdbRemoteTestCaseBase):
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# Pull out the register infos that we think we can bit flip successfully,.
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gpr_reg_infos = [reg_info for reg_info in reg_infos if self.is_bit_flippable_register(reg_info)]
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self.assertIsNotNone(len(gpr_reg_infos) > 0)
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self.assertTrue(len(gpr_reg_infos) > 0)
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# Write flipped bit pattern of existing value to each register.
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(successful_writes, failed_writes) = self.flip_all_bits_in_each_register_value(gpr_reg_infos, endian)
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@ -677,3 +677,178 @@ class GdbRemoteTestCaseBase(TestBase):
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self.assertIsNotNone(context.get("stop_signo"))
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self.assertIsNotNone(context.get("stop_key_val_text"))
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return (int(context["stop_signo"], 16), self.parse_key_val_dict(context["stop_key_val_text"]))
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def add_QSaveRegisterState_packets(self, thread_id):
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if thread_id:
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# Use the thread suffix form.
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request = "read packet: $QSaveRegisterState;thread:{:x}#00".format(thread_id)
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else:
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request = "read packet: $QSaveRegisterState#00"
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self.test_sequence.add_log_lines([
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request,
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{"direction":"send", "regex":r"^\$(E?.*)#[0-9a-fA-F]{2}$", "capture":{1:"save_response" } },
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], True)
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def parse_QSaveRegisterState_response(self, context):
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self.assertIsNotNone(context)
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save_response = context.get("save_response")
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self.assertIsNotNone(save_response)
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if len(save_response) < 1 or save_response[0] == "E":
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# error received
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return (False, None)
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else:
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return (True, int(save_response))
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def add_QRestoreRegisterState_packets(self, save_id, thread_id=None):
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if thread_id:
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# Use the thread suffix form.
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request = "read packet: $QRestoreRegisterState:{};thread:{:x}#00".format(save_id, thread_id)
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else:
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request = "read packet: $QRestoreRegisterState:{}#00".format(save_id)
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self.test_sequence.add_log_lines([
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request,
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"send packet: $OK#00"
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], True)
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def flip_all_bits_in_each_register_value(self, reg_infos, endian, thread_id=None):
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self.assertIsNotNone(reg_infos)
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successful_writes = 0
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failed_writes = 0
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for reg_info in reg_infos:
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# Use the lldb register index added to the reg info. We're not necessarily
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# working off a full set of register infos, so an inferred register index could be wrong.
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reg_index = reg_info["lldb_register_index"]
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self.assertIsNotNone(reg_index)
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reg_byte_size = int(reg_info["bitsize"])/8
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self.assertTrue(reg_byte_size > 0)
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# Handle thread suffix.
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if thread_id:
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p_request = "read packet: $p{:x};thread:{:x}#00".format(reg_index, thread_id)
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else:
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p_request = "read packet: $p{:x}#00".format(reg_index)
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# Read the existing value.
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self.reset_test_sequence()
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self.test_sequence.add_log_lines([
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p_request,
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{ "direction":"send", "regex":r"^\$([0-9a-fA-F]+)#", "capture":{1:"p_response"} },
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], True)
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context = self.expect_gdbremote_sequence()
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self.assertIsNotNone(context)
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# Verify the response length.
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p_response = context.get("p_response")
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self.assertIsNotNone(p_response)
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initial_reg_value = unpack_register_hex_unsigned(endian, p_response)
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# Flip the value by xoring with all 1s
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all_one_bits_raw = "ff" * (int(reg_info["bitsize"]) / 8)
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flipped_bits_int = initial_reg_value ^ int(all_one_bits_raw, 16)
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# print "reg (index={}, name={}): val={}, flipped bits (int={}, hex={:x})".format(reg_index, reg_info["name"], initial_reg_value, flipped_bits_int, flipped_bits_int)
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# Handle thread suffix for P.
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if thread_id:
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P_request = "read packet: $P{:x}={};thread:{:x}#00".format(reg_index, pack_register_hex(endian, flipped_bits_int, byte_size=reg_byte_size), thread_id)
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else:
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P_request = "read packet: $P{:x}={}#00".format(reg_index, pack_register_hex(endian, flipped_bits_int, byte_size=reg_byte_size))
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# Write the flipped value to the register.
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self.reset_test_sequence()
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self.test_sequence.add_log_lines([
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P_request,
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{ "direction":"send", "regex":r"^\$(OK|E[0-9a-fA-F]+)#[0-9a-fA-F]{2}", "capture":{1:"P_response"} },
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], True)
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context = self.expect_gdbremote_sequence()
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self.assertIsNotNone(context)
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# Determine if the write succeeded. There are a handful of registers that can fail, or partially fail
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# (e.g. flags, segment selectors, etc.) due to register value restrictions. Don't worry about them
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# all flipping perfectly.
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P_response = context.get("P_response")
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self.assertIsNotNone(P_response)
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if P_response == "OK":
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successful_writes += 1
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else:
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failed_writes += 1
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# print "reg (index={}, name={}) write FAILED (error: {})".format(reg_index, reg_info["name"], P_response)
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# Read back the register value, ensure it matches the flipped value.
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if P_response == "OK":
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self.reset_test_sequence()
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self.test_sequence.add_log_lines([
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p_request,
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{ "direction":"send", "regex":r"^\$([0-9a-fA-F]+)#", "capture":{1:"p_response"} },
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], True)
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context = self.expect_gdbremote_sequence()
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self.assertIsNotNone(context)
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verify_p_response_raw = context.get("p_response")
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self.assertIsNotNone(verify_p_response_raw)
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verify_bits = unpack_register_hex_unsigned(endian, verify_p_response_raw)
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if verify_bits != flipped_bits_int:
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# Some registers, like mxcsrmask and others, will permute what's written. Adjust succeed/fail counts.
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# print "reg (index={}, name={}): read verify FAILED: wrote {:x}, verify read back {:x}".format(reg_index, reg_info["name"], flipped_bits_int, verify_bits)
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successful_writes -= 1
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failed_writes +=1
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return (successful_writes, failed_writes)
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def is_bit_flippable_register(self, reg_info):
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if not reg_info:
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return False
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if not "set" in reg_info:
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return False
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if reg_info["set"] != "General Purpose Registers":
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return False
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if ("container-regs" in reg_info) and (len(reg_info["container-regs"]) > 0):
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# Don't try to bit flip registers contained in another register.
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return False
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if re.match("^.s$", reg_info["name"]):
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# This is a 2-letter register name that ends in "s", like a segment register.
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# Don't try to bit flip these.
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return False
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# Okay, this looks fine-enough.
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return True
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def read_register_values(self, reg_infos, endian, thread_id=None):
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self.assertIsNotNone(reg_infos)
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values = {}
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for reg_info in reg_infos:
|
||||
# We append a register index when load reg infos so we can work with subsets.
|
||||
reg_index = reg_info.get("lldb_register_index")
|
||||
self.assertIsNotNone(reg_index)
|
||||
|
||||
# Handle thread suffix.
|
||||
if thread_id:
|
||||
p_request = "read packet: $p{:x};thread:{:x}#00".format(reg_index, thread_id)
|
||||
else:
|
||||
p_request = "read packet: $p{:x}#00".format(reg_index)
|
||||
|
||||
# Read it with p.
|
||||
self.reset_test_sequence()
|
||||
self.test_sequence.add_log_lines([
|
||||
p_request,
|
||||
{ "direction":"send", "regex":r"^\$([0-9a-fA-F]+)#", "capture":{1:"p_response"} },
|
||||
], True)
|
||||
context = self.expect_gdbremote_sequence()
|
||||
self.assertIsNotNone(context)
|
||||
|
||||
# Convert value from target endian to integral.
|
||||
p_response = context.get("p_response")
|
||||
self.assertIsNotNone(p_response)
|
||||
self.assertTrue(len(p_response) > 0)
|
||||
self.assertFalse(p_response[0] == "E")
|
||||
|
||||
values[reg_index] = unpack_register_hex_unsigned(endian, p_response)
|
||||
|
||||
return values
|
||||
Loading…
Reference in New Issue