diff --git a/polly/lib/Transform/ZoneAlgo.cpp b/polly/lib/Transform/ZoneAlgo.cpp
index 1376bf111a76..d1dbdbeccdb0 100644
--- a/polly/lib/Transform/ZoneAlgo.cpp
+++ b/polly/lib/Transform/ZoneAlgo.cpp
@@ -446,30 +446,26 @@ void ZoneAlgorithm::addArrayWriteAccess(MemoryAccess *MA) {
   auto *Stmt = MA->getStatement();
 
   // { Domain[] -> Element[] }
-  auto AccRel = intersectRange(getAccessRelationFor(MA), CompatibleElts);
+  isl::map AccRel = intersectRange(getAccessRelationFor(MA), CompatibleElts);
 
   if (MA->isMustWrite())
-    AllMustWrites =
-        give(isl_union_map_add_map(AllMustWrites.take(), AccRel.copy()));
+    AllMustWrites = AllMustWrites.add_map(AccRel);
 
   if (MA->isMayWrite())
-    AllMayWrites =
-        give(isl_union_map_add_map(AllMayWrites.take(), AccRel.copy()));
+    AllMayWrites = AllMayWrites.add_map(AccRel);
 
   // { Domain[] -> ValInst[] }
-  auto WriteValInstance = getWrittenValue(MA, AccRel);
+  isl::map WriteValInstance = getWrittenValue(MA, AccRel);
   if (!WriteValInstance)
     WriteValInstance = makeUnknownForDomain(Stmt);
 
   // { Domain[] -> [Element[] -> Domain[]] }
-  auto IncludeElement = give(isl_map_curry(isl_map_domain_map(AccRel.copy())));
+  isl::map IncludeElement = AccRel.domain_map().curry();
 
   // { [Element[] -> DomainWrite[]] -> ValInst[] }
-  auto EltWriteValInst = give(
-      isl_map_apply_domain(WriteValInstance.take(), IncludeElement.take()));
+  isl::map EltWriteValInst = WriteValInstance.apply_domain(IncludeElement);
 
-  AllWriteValInst = give(
-      isl_union_map_add_map(AllWriteValInst.take(), EltWriteValInst.take()));
+  AllWriteValInst = AllWriteValInst.add_map(EltWriteValInst);
 }
 
 isl::union_set ZoneAlgorithm::makeEmptyUnionSet() const {