From 981f03e6a2202cdc2e245e1c6d5cec70d0dfdbf6 Mon Sep 17 00:00:00 2001 From: Adrian Prantl Date: Thu, 16 Mar 2017 17:14:56 +0000 Subject: [PATCH] PR32288: More efficient encoding for DWARF expr subregister access. Citing http://bugs.llvm.org/show_bug.cgi?id=32288 The DWARF generated by LLVM includes this location: 0x55 0x93 0x04 DW_OP_reg5 DW_OP_piece(4) When GCC's DWARF is simply 0x55 (DW_OP_reg5) without the DW_OP_piece. I believe it's reasonable to assume the DWARF consumer knows which part of a register logically holds the value (low bytes, high bytes, how many bytes, etc) for a primitive value like an integer. This patch gets rid of the redundant DW_OP_piece when a subregister is at offset 0. It also adds previously missing subregister masking when a subregister is followed by another operation. (This reapplies r297960 with two additional testcase updates). rdar://problem/31069390 https://reviews.llvm.org/D31010 llvm-svn: 297965 --- .../CodeGen/AsmPrinter/DwarfExpression.cpp | 31 +++++++++++++++++-- llvm/lib/CodeGen/AsmPrinter/DwarfExpression.h | 7 ++++- llvm/test/CodeGen/ARM/debug-info-s16-reg.ll | 2 -- llvm/test/CodeGen/ARM/debug-info-sreg2.ll | 2 +- llvm/test/DebugInfo/ARM/s-super-register.ll | 4 +-- llvm/test/DebugInfo/X86/PR26148.ll | 2 +- .../DebugInfo/X86/dbg-value-const-byref.ll | 4 +-- .../X86/dbg-value-regmask-clobber.ll | 6 ++-- llvm/test/DebugInfo/X86/dw_op_minus_direct.ll | 4 +-- llvm/test/DebugInfo/X86/fission-ranges.ll | 8 ++--- llvm/test/DebugInfo/X86/single-dbg_value.ll | 4 +-- llvm/test/DebugInfo/X86/subreg.ll | 5 +-- llvm/test/DebugInfo/X86/subregisters.ll | 6 ++-- 13 files changed, 56 insertions(+), 29 deletions(-) diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp index 43c98442d8b2..caf0bc0f2585 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp @@ -66,6 +66,12 @@ void DwarfExpression::AddShr(unsigned ShiftBy) { EmitOp(dwarf::DW_OP_shr); } +void DwarfExpression::AddAnd(unsigned Mask) { + EmitOp(dwarf::DW_OP_constu); + EmitUnsigned(Mask); + EmitOp(dwarf::DW_OP_and); +} + bool DwarfExpression::AddMachineRegIndirect(const TargetRegisterInfo &TRI, unsigned MachineReg, int Offset) { if (isFrameRegister(TRI, MachineReg)) { @@ -230,6 +236,12 @@ void DwarfExpression::AddExpression(DIExpressionCursor &&ExprCursor, unsigned FragmentOffsetInBits) { while (ExprCursor) { auto Op = ExprCursor.take(); + + // If we need to mask out a subregister, do it now, unless the next + // operation would emit an OpPiece anyway. + if (SubRegisterSizeInBits && Op->getOp() != dwarf::DW_OP_LLVM_fragment) + maskSubRegister(); + switch (Op->getOp()) { case dwarf::DW_OP_LLVM_fragment: { unsigned SizeInBits = Op->getArg(1); @@ -285,9 +297,24 @@ void DwarfExpression::AddExpression(DIExpressionCursor &&ExprCursor, } } +/// Add masking operations to stencil out a subregister. +void DwarfExpression::maskSubRegister() { + assert(SubRegisterSizeInBits && "no subregister was registered"); + if (SubRegisterOffsetInBits > 0) + AddShr(SubRegisterOffsetInBits); + uint64_t Mask = (1UL << SubRegisterSizeInBits) - 1; + AddAnd(Mask); +} + + void DwarfExpression::finalize() { - if (SubRegisterSizeInBits) - AddOpPiece(SubRegisterSizeInBits, SubRegisterOffsetInBits); + // Emit any outstanding DW_OP_piece operations to mask out subregisters. + if (SubRegisterSizeInBits == 0) + return; + // Don't emit a DW_OP_piece for a subregister at offset 0. + if (SubRegisterOffsetInBits == 0) + return; + AddOpPiece(SubRegisterSizeInBits, SubRegisterOffsetInBits); } void DwarfExpression::addFragmentOffset(const DIExpression *Expr) { diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.h b/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.h index 01f66fa7eac4..2f5a701499dd 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.h +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.h @@ -99,6 +99,9 @@ protected: SubRegisterOffsetInBits = OffsetInBits; } + /// Add masking operations to stencil out a subregister. + void maskSubRegister(); + public: DwarfExpression(unsigned DwarfVersion) : DwarfVersion(DwarfVersion) {} virtual ~DwarfExpression() {}; @@ -126,8 +129,10 @@ public: /// is at the top of the DWARF stack. void AddOpPiece(unsigned SizeInBits, unsigned OffsetInBits = 0); - /// Emit a shift-right dwarf expression. + /// Emit a shift-right dwarf operation. void AddShr(unsigned ShiftBy); + /// Emit a bitwise and dwarf operation. + void AddAnd(unsigned Mask); /// Emit a DW_OP_stack_value, if supported. /// diff --git a/llvm/test/CodeGen/ARM/debug-info-s16-reg.ll b/llvm/test/CodeGen/ARM/debug-info-s16-reg.ll index 2987b9a2105a..197746c5f122 100644 --- a/llvm/test/CodeGen/ARM/debug-info-s16-reg.ll +++ b/llvm/test/CodeGen/ARM/debug-info-s16-reg.ll @@ -3,8 +3,6 @@ ; Test dwarf reg no for s16 ;CHECK: super-register DW_OP_regx ;CHECK-NEXT: 264 -;CHECK-NEXT: DW_OP_piece -;CHECK-NEXT: 4 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" target triple = "thumbv7-apple-macosx10.6.7" diff --git a/llvm/test/CodeGen/ARM/debug-info-sreg2.ll b/llvm/test/CodeGen/ARM/debug-info-sreg2.ll index b31d1b7bed4f..094b10499788 100644 --- a/llvm/test/CodeGen/ARM/debug-info-sreg2.ll +++ b/llvm/test/CodeGen/ARM/debug-info-sreg2.ll @@ -10,7 +10,7 @@ target triple = "thumbv7-apple-macosx10.6.7" ; CHECK: 0x00000000: Beginning address offset: ; CHECK-NEXT: Ending address offset: -; CHECK-NEXT: Location description: 90 {{.. .. .. .. $}} +; CHECK-NEXT: Location description: 90 {{.. .. $}} define void @_Z3foov() optsize ssp !dbg !1 { entry: diff --git a/llvm/test/DebugInfo/ARM/s-super-register.ll b/llvm/test/DebugInfo/ARM/s-super-register.ll index ef2bc9ac1ec3..de0284a9a557 100644 --- a/llvm/test/DebugInfo/ARM/s-super-register.ll +++ b/llvm/test/DebugInfo/ARM/s-super-register.ll @@ -5,9 +5,7 @@ target triple = "thumbv7-apple-macosx10.6.7" ; The S registers on ARM are expressed as pieces of their super-registers in DWARF. ; ; 0x90 DW_OP_regx of super-register -; 0x93 DW_OP_piece -; 0x9d DW_OP_bit_piece -; CHECK: Location description: 90 {{.. .. ((93 ..)|(9d .. ..)) $}} +; CHECK: Location description: 90 define void @_Z3foov() optsize ssp !dbg !1 { entry: diff --git a/llvm/test/DebugInfo/X86/PR26148.ll b/llvm/test/DebugInfo/X86/PR26148.ll index 1f66b7599faa..69e7bbd213b4 100644 --- a/llvm/test/DebugInfo/X86/PR26148.ll +++ b/llvm/test/DebugInfo/X86/PR26148.ll @@ -19,7 +19,7 @@ ; AS in 26163, we expect two ranges (as opposed to one), the first one being zero sized ; ; -; CHECK: 0x00000025: Beginning address offset: 0x0000000000000004 +; CHECK: Beginning address offset: 0x0000000000000004 ; CHECK: Ending address offset: 0x0000000000000004 ; CHECK: Location description: 10 03 93 04 55 93 02 ; constu 0x00000003, piece 0x00000004, rdi, piece 0x00000002 diff --git a/llvm/test/DebugInfo/X86/dbg-value-const-byref.ll b/llvm/test/DebugInfo/X86/dbg-value-const-byref.ll index 40b9f726f31e..77e243702a8a 100644 --- a/llvm/test/DebugInfo/X86/dbg-value-const-byref.ll +++ b/llvm/test/DebugInfo/X86/dbg-value-const-byref.ll @@ -34,10 +34,10 @@ ; CHECK: Beginning address offset: [[C1]] ; CHECK: Ending address offset: [[C2:.*]] ; CHECK: Location description: 11 07 -; rax, piece 0x00000004 +; rax ; CHECK: Beginning address offset: [[C2]] ; CHECK: Ending address offset: [[R1:.*]] -; CHECK: Location description: 50 93 04 +; CHECK: Location description: 50 ; rdi+0 ; CHECK: Beginning address offset: [[R1]] ; CHECK: Ending address offset: [[R2:.*]] diff --git a/llvm/test/DebugInfo/X86/dbg-value-regmask-clobber.ll b/llvm/test/DebugInfo/X86/dbg-value-regmask-clobber.ll index 93543e5ed948..b958f080d02e 100644 --- a/llvm/test/DebugInfo/X86/dbg-value-regmask-clobber.ll +++ b/llvm/test/DebugInfo/X86/dbg-value-regmask-clobber.ll @@ -16,10 +16,8 @@ ; ASM: .Ldebug_loc1: ; ASM-NEXT: .quad .Lfunc_begin0-.Lfunc_begin0 ; ASM-NEXT: .quad [[argc_range_end]]-.Lfunc_begin0 -; ASM-NEXT: .short 3 # Loc expr size +; ASM-NEXT: .short 1 # Loc expr size ; ASM-NEXT: .byte 82 # super-register DW_OP_reg2 -; ASM-NEXT: .byte 147 # DW_OP_piece -; ASM-NEXT: .byte 4 # 4 ; argc is the first formal parameter. ; DWARF: .debug_info contents: @@ -30,7 +28,7 @@ ; DWARF: .debug_loc contents: ; DWARF: [[argc_loc_offset]]: Beginning address offset: 0x0000000000000000 ; DWARF-NEXT: Ending address offset: 0x0000000000000013 -; DWARF-NEXT: Location description: 52 93 04 +; DWARF-NEXT: Location description: 52 ; ModuleID = 't.cpp' source_filename = "test/DebugInfo/X86/dbg-value-regmask-clobber.ll" diff --git a/llvm/test/DebugInfo/X86/dw_op_minus_direct.ll b/llvm/test/DebugInfo/X86/dw_op_minus_direct.ll index a84c506b90a7..29e07213abbb 100644 --- a/llvm/test/DebugInfo/X86/dw_op_minus_direct.ll +++ b/llvm/test/DebugInfo/X86/dw_op_minus_direct.ll @@ -8,8 +8,8 @@ ; CHECK: Beginning address offset: 0x0000000000000000 ; CHECK: Ending address offset: 0x0000000000000004 -; CHECK: Location description: 50 10 01 1c 93 04 -; rax, constu 0x00000001, minus, piece 0x00000004 +; CHECK: Location description: 50 10 ff ff ff ff 0f 1a 10 01 1c +; rax, constu 0xffffffff, and, constu 0x00000001, minus source_filename = "minus.c" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.12.0" diff --git a/llvm/test/DebugInfo/X86/fission-ranges.ll b/llvm/test/DebugInfo/X86/fission-ranges.ll index 0dfb13ab66b7..60d0f1777a43 100644 --- a/llvm/test/DebugInfo/X86/fission-ranges.ll +++ b/llvm/test/DebugInfo/X86/fission-ranges.ll @@ -30,16 +30,16 @@ ; CHECK-NEXT: {{^$}} ; CHECK-NEXT: Beginning address index: 3 ; CHECK-NEXT: Length: 25 -; CHECK-NEXT: Location description: 50 93 04 +; CHECK-NEXT: Location description: 50 ; CHECK: [[E]]: Beginning address index: 4 ; CHECK-NEXT: Length: 19 -; CHECK-NEXT: Location description: 50 93 04 +; CHECK-NEXT: Location description: 50 ; CHECK: [[B]]: Beginning address index: 5 ; CHECK-NEXT: Length: 17 -; CHECK-NEXT: Location description: 50 93 04 +; CHECK-NEXT: Location description: 50 ; CHECK: [[D]]: Beginning address index: 6 ; CHECK-NEXT: Length: 17 -; CHECK-NEXT: Location description: 50 93 04 +; CHECK-NEXT: Location description: 50 ; Make sure we don't produce any relocations in any .dwo section (though in particular, debug_info.dwo) ; HDR-NOT: .rela.{{.*}}.dwo diff --git a/llvm/test/DebugInfo/X86/single-dbg_value.ll b/llvm/test/DebugInfo/X86/single-dbg_value.ll index 0275c37d24e7..7f77e61092db 100644 --- a/llvm/test/DebugInfo/X86/single-dbg_value.ll +++ b/llvm/test/DebugInfo/X86/single-dbg_value.ll @@ -8,8 +8,8 @@ ; CHECK-NEXT: DW_AT_location [DW_FORM_data4] ; CHECK-NEXT: DW_AT_name{{.*}}"a" ; CHECK: .debug_loc contents: -; rax, piece 0x00000004 -; CHECK: Location description: 50 93 04 +; rax +; CHECK: Location description: 50 ; SANITY: DBG_VALUE ; SANITY-NOT: DBG_VALUE ; ModuleID = 'test.ll' diff --git a/llvm/test/DebugInfo/X86/subreg.ll b/llvm/test/DebugInfo/X86/subreg.ll index 5e837edfd2bf..30c672396e4e 100644 --- a/llvm/test/DebugInfo/X86/subreg.ll +++ b/llvm/test/DebugInfo/X86/subreg.ll @@ -4,8 +4,9 @@ ; being in its superregister. ; CHECK: .byte 80 # super-register DW_OP_reg0 -; CHECK-NEXT: .byte 147 # DW_OP_piece -; CHECK-NEXT: .byte 2 # 2 +; No need to a piece at offset 0. +; CHECK-NOT: DW_OP_piece +; CHECK-NOT: DW_OP_bit_piece define i16 @f(i16 signext %zzz) nounwind !dbg !1 { entry: diff --git a/llvm/test/DebugInfo/X86/subregisters.ll b/llvm/test/DebugInfo/X86/subregisters.ll index d40be0d9e3c1..99f7a10e443b 100644 --- a/llvm/test/DebugInfo/X86/subregisters.ll +++ b/llvm/test/DebugInfo/X86/subregisters.ll @@ -2,7 +2,7 @@ ; RUN: llvm-dwarfdump %t.o | FileCheck %s ; ; Test that on x86_64, the 32-bit subregister esi is emitted as -; DW_OP_piece 32 of the 64-bit rsi. +; subregister of the 64-bit rsi. ; ; rdar://problem/16015314 ; @@ -11,8 +11,8 @@ ; CHECK-NEXT: DW_AT_location [DW_FORM_data4] (0x00000000) ; CHECK-NEXT: DW_AT_name [DW_FORM_strp]{{.*}} "a" ; CHECK: .debug_loc contents: -; rsi, piece 0x00000004 -; CHECK: Location description: 54 93 04 +; rsi +; CHECK: Location description: 54 ; ; struct bar { ; int a;