forked from OSchip/llvm-project
Fix a bug in the scheduler's handling of "unspillable" vregs.
Imagine we see: EFLAGS = inst1 EFLAGS = inst2 FLAGS gpr = inst3 EFLAGS Previously, we would refuse to schedule inst2 because it clobbers the EFLAGS of the predecessor. However, it also uses the EFLAGS of the predecessor, so it is safe to emit. SDep edges ensure that the right order happens already anyway. This fixes 2 testsuite crashes with the X86 patch I'm going to commit next. llvm-svn: 122211
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@ -704,6 +704,19 @@ DelayForLiveRegsBottomUp(SUnit *SU, SmallVector<unsigned, 4> &LRegs) {
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}
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// Okay, we now know all of the live registers that are defined by an
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// immediate predecessor. It is ok to kill these registers if we are also
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// using it.
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for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I) {
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if (I->isAssignedRegDep() &&
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LiveRegCycles[I->getReg()] == I->getSUnit()->getHeight()) {
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unsigned Reg = I->getReg();
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if (RegAdded.erase(Reg))
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LRegs.erase(std::find(LRegs.begin(), LRegs.end(), Reg));
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}
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}
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return !LRegs.empty();
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}
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