From 981afd206bf8e3113099f57ca0ec0da68ff3ce08 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Mon, 20 Dec 2010 00:55:43 +0000 Subject: [PATCH] Fix a bug in the scheduler's handling of "unspillable" vregs. Imagine we see: EFLAGS = inst1 EFLAGS = inst2 FLAGS gpr = inst3 EFLAGS Previously, we would refuse to schedule inst2 because it clobbers the EFLAGS of the predecessor. However, it also uses the EFLAGS of the predecessor, so it is safe to emit. SDep edges ensure that the right order happens already anyway. This fixes 2 testsuite crashes with the X86 patch I'm going to commit next. llvm-svn: 122211 --- .../CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 0f4d9c826785..72bfe7195d6c 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -283,7 +283,7 @@ void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) { Sequence.push_back(SU); AvailableQueue->ScheduledNode(SU); - + ReleasePredecessors(SU, CurCycle); // Release all the implicit physical register defs that are live. @@ -704,6 +704,19 @@ DelayForLiveRegsBottomUp(SUnit *SU, SmallVector &LRegs) { } + // Okay, we now know all of the live registers that are defined by an + // immediate predecessor. It is ok to kill these registers if we are also + // using it. + for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); + I != E; ++I) { + if (I->isAssignedRegDep() && + LiveRegCycles[I->getReg()] == I->getSUnit()->getHeight()) { + unsigned Reg = I->getReg(); + if (RegAdded.erase(Reg)) + LRegs.erase(std::find(LRegs.begin(), LRegs.end(), Reg)); + } + } + return !LRegs.empty(); }