forked from OSchip/llvm-project
AVX-512: added extend and truncate instructions.
llvm-svn: 189580
This commit is contained in:
Elena Demikhovsky
parent
ab7ff52efd
commit
980c6b08b1
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@ -8856,6 +8856,37 @@ static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
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return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
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}
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static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
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SelectionDAG &DAG) {
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MVT VT = Op->getValueType(0).getSimpleVT();
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SDValue In = Op->getOperand(0);
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MVT InVT = In.getValueType().getSimpleVT();
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SDLoc DL(Op);
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unsigned int NumElts = VT.getVectorNumElements();
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if (NumElts != 8 && NumElts != 16)
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return SDValue();
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if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
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return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
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EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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// Now we have only mask extension
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assert(InVT.getVectorElementType() == MVT::i1);
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SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
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const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
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SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
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unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
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SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
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MachinePointerInfo::getConstantPool(),
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false, false, false, Alignment);
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SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
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if (VT.is512BitVector())
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return Brcst;
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return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
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}
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static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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if (Subtarget->hasFp256()) {
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@ -8874,6 +8905,9 @@ static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
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SDValue In = Op.getOperand(0);
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MVT SVT = In.getSimpleValueType();
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if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
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return LowerZERO_EXTEND_AVX512(Op, DAG);
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if (Subtarget->hasFp256()) {
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SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
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if (Res.getNode())
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@ -8902,11 +8936,37 @@ static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
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SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
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SDLoc DL(Op);
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MVT VT = Op.getSimpleValueType();
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MVT VT = Op.getSimpleValueType();
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SDValue In = Op.getOperand(0);
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MVT SVT = In.getSimpleValueType();
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MVT InVT = In.getSimpleValueType();
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assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
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"Invalid TRUNCATE operation");
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if ((VT == MVT::v4i32) && (SVT == MVT::v4i64)) {
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if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
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if (VT.getVectorElementType().getSizeInBits() >=8)
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return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
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assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
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unsigned NumElts = InVT.getVectorNumElements();
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assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
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if (InVT.getSizeInBits() < 512) {
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MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
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In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
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InVT = ExtVT;
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}
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SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
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const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
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SDValue CP = DAG.getConstantPool(C, getPointerTy());
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unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
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SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
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MachinePointerInfo::getConstantPool(),
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false, false, false, Alignment);
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SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
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SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
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return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
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}
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if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
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// On AVX2, v4i64 -> v4i32 becomes VPERMD.
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if (Subtarget->hasInt256()) {
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static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
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@ -8937,7 +8997,7 @@ SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
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return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
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}
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if ((VT == MVT::v8i16) && (SVT == MVT::v8i32)) {
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if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
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// On AVX2, v8i32 -> v8i16 becomed PSHUFB.
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if (Subtarget->hasInt256()) {
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In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
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@ -8995,11 +9055,9 @@ SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
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}
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// Handle truncation of V256 to V128 using shuffles.
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if (!VT.is128BitVector() || !SVT.is256BitVector())
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if (!VT.is128BitVector() || !InVT.is256BitVector())
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return SDValue();
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assert(VT.getVectorNumElements() != SVT.getVectorNumElements() &&
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"Invalid op");
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assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
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unsigned NumElems = VT.getVectorNumElements();
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@ -10282,28 +10340,29 @@ static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
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MVT InVT = In.getSimpleValueType();
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SDLoc dl(Op);
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if (InVT.getVectorElementType().getSizeInBits() >=8 &&
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VT.getVectorElementType().getSizeInBits() >= 32)
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unsigned int NumElts = VT.getVectorNumElements();
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if (NumElts != 8 && NumElts != 16)
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return SDValue();
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if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
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return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
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if (InVT.getVectorElementType() == MVT::i1) {
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unsigned int NumElts = InVT.getVectorNumElements();
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assert ((NumElts == 8 || NumElts == 16) &&
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"Unsupported SIGN_EXTEND operation");
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if (VT.getVectorElementType().getSizeInBits() >= 32) {
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Constant *C =
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ConstantInt::get(*DAG.getContext(),
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(NumElts == 8)? APInt(64, ~0ULL): APInt(32, ~0U));
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
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unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
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SDValue Ld = DAG.getLoad(VT.getScalarType(), dl, DAG.getEntryNode(), CP,
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MachinePointerInfo::getConstantPool(),
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false, false, false, Alignment);
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return DAG.getNode(X86ISD::VBROADCASTM, dl, VT, In, Ld);
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}
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}
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return SDValue();
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
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MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
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Constant *C = ConstantInt::get(*DAG.getContext(),
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APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
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SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
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unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
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SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
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MachinePointerInfo::getConstantPool(),
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false, false, false, Alignment);
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SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
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if (VT.is512BitVector())
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return Brcst;
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return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
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}
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static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
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@ -11142,10 +11201,14 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
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case Intrinsic::x86_sse2_max_pd:
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case Intrinsic::x86_avx_max_ps_256:
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case Intrinsic::x86_avx_max_pd_256:
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case Intrinsic::x86_avx512_max_ps_512:
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case Intrinsic::x86_avx512_max_pd_512:
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case Intrinsic::x86_sse_min_ps:
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case Intrinsic::x86_sse2_min_pd:
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case Intrinsic::x86_avx_min_ps_256:
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case Intrinsic::x86_avx_min_pd_256: {
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case Intrinsic::x86_avx_min_pd_256:
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case Intrinsic::x86_avx512_min_ps_512:
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case Intrinsic::x86_avx512_min_pd_512: {
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unsigned Opcode;
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switch (IntNo) {
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default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
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@ -11153,12 +11216,16 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
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case Intrinsic::x86_sse2_max_pd:
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case Intrinsic::x86_avx_max_ps_256:
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case Intrinsic::x86_avx_max_pd_256:
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case Intrinsic::x86_avx512_max_ps_512:
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case Intrinsic::x86_avx512_max_pd_512:
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Opcode = X86ISD::FMAX;
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break;
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case Intrinsic::x86_sse_min_ps:
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case Intrinsic::x86_sse2_min_pd:
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case Intrinsic::x86_avx_min_ps_256:
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case Intrinsic::x86_avx_min_pd_256:
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case Intrinsic::x86_avx512_min_ps_512:
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case Intrinsic::x86_avx512_min_pd_512:
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Opcode = X86ISD::FMIN;
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break;
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}
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@ -13375,6 +13442,8 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
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case X86ISD::VZEXT: return "X86ISD::VZEXT";
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case X86ISD::VSEXT: return "X86ISD::VSEXT";
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case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
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case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
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case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
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case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
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case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
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@ -16274,6 +16343,23 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
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return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
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}
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if (Subtarget->hasAVX512() && VT.isVector() &&
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Cond.getValueType().getVectorElementType() == MVT::i1) {
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// v16i8 (select v16i1, v16i8, v16i8) does not have a proper
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// lowering on AVX-512. In this case we convert it to
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// v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
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// The same situation for all 128 and 256-bit vectors of i8 and i16
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EVT OpVT = LHS.getValueType();
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if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
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(OpVT.getVectorElementType() == MVT::i8 ||
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OpVT.getVectorElementType() == MVT::i16)) {
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Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
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DCI.AddToWorklist(Cond.getNode());
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return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
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}
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else
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return SDValue();
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}
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// If this is a select between two integer constants, try to do some
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// optimizations.
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if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
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@ -254,6 +254,12 @@ namespace llvm {
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// VSEXT - Vector integer signed-extend.
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VSEXT,
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// VTRUNC - Vector integer truncate.
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VTRUNC,
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// VTRUNC - Vector integer truncate with mask.
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VTRUNCM,
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// VFPEXT - Vector FP extend.
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VFPEXT,
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@ -2805,6 +2805,123 @@ def : Pat<(v8f64 (frint VR512:$src)),
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def : Pat<(v8f64 (ftrunc VR512:$src)),
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(VRNDSCALEZPDr VR512:$src, (i32 0x3))>;
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//-------------------------------------------------
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// Integer truncate and extend operations
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//-------------------------------------------------
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multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
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RegisterClass dstRC, RegisterClass srcRC,
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RegisterClass KRC, X86MemOperand x86memop> {
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def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
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(ins srcRC:$src),
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!strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
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[]>, EVEX;
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def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
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(ins KRC:$mask, srcRC:$src),
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!strconcat(OpcodeStr,
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"\t{$src, ${dst}{${mask}}{z}|${dst}{${mask}}{z}, $src}"),
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[]>, EVEX, EVEX_KZ;
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def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[]>, EVEX;
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}
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defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
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i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
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defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
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i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
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defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
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i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
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defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
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i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
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defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
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i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
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defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
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i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
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defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
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i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
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defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
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i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
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defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
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i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
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defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
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i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
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defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
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i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
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defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
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i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
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defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
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i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
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defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
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i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
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defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
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i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
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def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
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def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
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def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
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def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
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def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
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def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
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(VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
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def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
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(VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
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def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
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(VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
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def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
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(VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
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multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
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RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
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X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
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def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
|
||||
(ins SrcRC:$src),
|
||||
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
||||
[(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
|
||||
def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
|
||||
(ins x86memop:$src),
|
||||
!strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
|
||||
[(set DstRC:$dst,
|
||||
(OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
|
||||
EVEX;
|
||||
}
|
||||
|
||||
defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
|
||||
memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
|
||||
EVEX_CD8<8, CD8VQ>;
|
||||
defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
|
||||
memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
|
||||
EVEX_CD8<8, CD8VO>;
|
||||
defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
|
||||
memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
|
||||
EVEX_CD8<16, CD8VH>;
|
||||
defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
|
||||
memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
|
||||
EVEX_CD8<16, CD8VQ>;
|
||||
defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
|
||||
memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
|
||||
EVEX_CD8<32, CD8VH>;
|
||||
|
||||
defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
|
||||
memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
|
||||
EVEX_CD8<8, CD8VQ>;
|
||||
defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
|
||||
memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
|
||||
EVEX_CD8<8, CD8VO>;
|
||||
defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
|
||||
memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
|
||||
EVEX_CD8<16, CD8VH>;
|
||||
defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
|
||||
memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
|
||||
EVEX_CD8<16, CD8VQ>;
|
||||
defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
|
||||
memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
|
||||
EVEX_CD8<32, CD8VH>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// VSHUFPS - VSHUFPD Operations
|
||||
|
||||
|
|
|
|||
|
|
@ -105,6 +105,13 @@ def X86vsext : SDNode<"X86ISD::VSEXT",
|
|||
SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
|
||||
SDTCisInt<0>, SDTCisInt<1>]>>;
|
||||
|
||||
def X86vtrunc : SDNode<"X86ISD::VTRUNC",
|
||||
SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
|
||||
SDTCisInt<0>, SDTCisInt<1>]>>;
|
||||
def X86vtruncm : SDNode<"X86ISD::VTRUNCM",
|
||||
SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
|
||||
SDTCisInt<0>, SDTCisInt<1>,
|
||||
SDTCisVec<2>, SDTCisInt<2>]>>;
|
||||
def X86vfpext : SDNode<"X86ISD::VFPEXT",
|
||||
SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
|
||||
SDTCisFP<0>, SDTCisFP<1>]>>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,127 @@
|
|||
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
|
||||
|
||||
; CHECK-LABEL: trunc_16x32_to_16x8
|
||||
; CHECK: vpmovdb
|
||||
; CHECK: ret
|
||||
define <16 x i8> @trunc_16x32_to_16x8(<16 x i32> %i) nounwind readnone {
|
||||
%x = trunc <16 x i32> %i to <16 x i8>
|
||||
ret <16 x i8> %x
|
||||
}
|
||||
|
||||
; CHECK-LABEL: trunc_8x64_to_8x16
|
||||
; CHECK: vpmovqw
|
||||
; CHECK: ret
|
||||
define <8 x i16> @trunc_8x64_to_8x16(<8 x i64> %i) nounwind readnone {
|
||||
%x = trunc <8 x i64> %i to <8 x i16>
|
||||
ret <8 x i16> %x
|
||||
}
|
||||
|
||||
|
||||
; CHECK-LABEL: zext_16x8_to_16x32
|
||||
; CHECK; vpmovzxbd {{.*}}%zmm
|
||||
; CHECK: ret
|
||||
define <16 x i32> @zext_16x8_to_16x32(<16 x i8> %i) nounwind readnone {
|
||||
%x = zext <16 x i8> %i to <16 x i32>
|
||||
ret <16 x i32> %x
|
||||
}
|
||||
|
||||
; CHECK-LABEL: sext_16x8_to_16x32
|
||||
; CHECK; vpmovsxbd {{.*}}%zmm
|
||||
; CHECK: ret
|
||||
define <16 x i32> @sext_16x8_to_16x32(<16 x i8> %i) nounwind readnone {
|
||||
%x = sext <16 x i8> %i to <16 x i32>
|
||||
ret <16 x i32> %x
|
||||
}
|
||||
|
||||
|
||||
; CHECK-LABEL: zext_16x16_to_16x32
|
||||
; CHECK; vpmovzxwd {{.*}}%zmm
|
||||
; CHECK: ret
|
||||
define <16 x i32> @zext_16x16_to_16x32(<16 x i16> %i) nounwind readnone {
|
||||
%x = zext <16 x i16> %i to <16 x i32>
|
||||
ret <16 x i32> %x
|
||||
}
|
||||
|
||||
; CHECK-LABEL: zext_8x16_to_8x64
|
||||
; CHECK; vpmovzxwq
|
||||
; CHECK: ret
|
||||
define <8 x i64> @zext_8x16_to_8x64(<8 x i16> %i) nounwind readnone {
|
||||
%x = zext <8 x i16> %i to <8 x i64>
|
||||
ret <8 x i64> %x
|
||||
}
|
||||
|
||||
;CHECK-LABEL: fptrunc_test
|
||||
;CHECK: vcvtpd2ps {{.*}}%zmm
|
||||
;CHECK: ret
|
||||
define <8 x float> @fptrunc_test(<8 x double> %a) nounwind readnone {
|
||||
%b = fptrunc <8 x double> %a to <8 x float>
|
||||
ret <8 x float> %b
|
||||
}
|
||||
|
||||
;CHECK-LABEL: fpext_test
|
||||
;CHECK: vcvtps2pd {{.*}}%zmm
|
||||
;CHECK: ret
|
||||
define <8 x double> @fpext_test(<8 x float> %a) nounwind readnone {
|
||||
%b = fpext <8 x float> %a to <8 x double>
|
||||
ret <8 x double> %b
|
||||
}
|
||||
|
||||
; CHECK-LABEL: zext_16i1_to_16xi32
|
||||
; CHECK: vpbroadcastd LCP{{.*}}(%rip), %zmm0{%k1}{z}
|
||||
; CHECK: ret
|
||||
define <16 x i32> @zext_16i1_to_16xi32(i16 %b) {
|
||||
%a = bitcast i16 %b to <16 x i1>
|
||||
%c = zext <16 x i1> %a to <16 x i32>
|
||||
ret <16 x i32> %c
|
||||
}
|
||||
|
||||
; CHECK-LABEL: zext_8i1_to_8xi64
|
||||
; CHECK: vpbroadcastq LCP{{.*}}(%rip), %zmm0{%k1}{z}
|
||||
; CHECK: ret
|
||||
define <8 x i64> @zext_8i1_to_8xi64(i8 %b) {
|
||||
%a = bitcast i8 %b to <8 x i1>
|
||||
%c = zext <8 x i1> %a to <8 x i64>
|
||||
ret <8 x i64> %c
|
||||
}
|
||||
|
||||
; CHECK-LABEL: trunc_16i8_to_16i1
|
||||
; CHECK: vpmovsxbd
|
||||
; CHECK: vpandd
|
||||
; CHECK: vptestmd
|
||||
; CHECK: ret
|
||||
define i16 @trunc_16i8_to_16i1(<16 x i8> %a) {
|
||||
%mask_b = trunc <16 x i8>%a to <16 x i1>
|
||||
%mask = bitcast <16 x i1> %mask_b to i16
|
||||
ret i16 %mask
|
||||
}
|
||||
|
||||
; CHECK-LABEL: trunc_16i32_to_16i1
|
||||
; CHECK: vpandd
|
||||
; CHECK: vptestmd
|
||||
; CHECK: ret
|
||||
define i16 @trunc_16i32_to_16i1(<16 x i32> %a) {
|
||||
%mask_b = trunc <16 x i32>%a to <16 x i1>
|
||||
%mask = bitcast <16 x i1> %mask_b to i16
|
||||
ret i16 %mask
|
||||
}
|
||||
|
||||
; CHECK-LABEL: trunc_8i16_to_8i1
|
||||
; CHECK: vpmovsxwq
|
||||
; CHECK: vpandq LCP{{.*}}(%rip){1to8}
|
||||
; CHECK: vptestmq
|
||||
; CHECK: ret
|
||||
define i8 @trunc_8i16_to_8i1(<8 x i16> %a) {
|
||||
%mask_b = trunc <8 x i16>%a to <8 x i1>
|
||||
%mask = bitcast <8 x i1> %mask_b to i8
|
||||
ret i8 %mask
|
||||
}
|
||||
|
||||
; CHECK: sext_8i1_8i32
|
||||
; CHECK: vpbroadcastq LCP{{.*}}(%rip), %zmm0{%k1}{z}
|
||||
; CHECK: ret
|
||||
define <8 x i32> @sext_8i1_8i32(<8 x i32> %a1, <8 x i32> %a2) nounwind {
|
||||
%x = icmp slt <8 x i32> %a1, %a2
|
||||
%x1 = xor <8 x i1>%x, <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
|
||||
%y = sext <8 x i1> %x1 to <8 x i32>
|
||||
ret <8 x i32> %y
|
||||
}
|
||||
Loading…
Reference in New Issue