forked from OSchip/llvm-project
[ELF] Implement RISCV::getImplicitAddend()
This allows checking dynamic relocation addends for -z rel and --apply-dynamic-relocs output. Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D101455
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@ -24,6 +24,7 @@ class RISCV final : public TargetInfo {
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public:
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RISCV();
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uint32_t calcEFlags() const override;
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int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;
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void writeGotHeader(uint8_t *buf) const override;
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void writeGotPlt(uint8_t *buf, const Symbol &s) const override;
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void writeIgotPlt(uint8_t *buf, const Symbol &s) const override;
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@ -134,6 +135,28 @@ uint32_t RISCV::calcEFlags() const {
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return target;
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}
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int64_t RISCV::getImplicitAddend(const uint8_t *buf, RelType type) const {
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switch (type) {
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default:
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internalLinkerError(getErrorLocation(buf),
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"cannot read addend for relocation " + toString(type));
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return 0;
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case R_RISCV_32:
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case R_RISCV_TLS_DTPMOD32:
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case R_RISCV_TLS_DTPREL32:
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return SignExtend64<32>(read32le(buf));
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case R_RISCV_64:
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return read64le(buf);
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case R_RISCV_RELATIVE:
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case R_RISCV_IRELATIVE:
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return config->is64 ? read64le(buf) : read32le(buf);
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case R_RISCV_NONE:
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case R_RISCV_JUMP_SLOT:
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// These relocations are defined as not having an implicit addend.
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return 0;
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}
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}
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void RISCV::writeGotHeader(uint8_t *buf) const {
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if (config->is64)
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write64le(buf, mainPart->dynamic->getVA());
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@ -1400,8 +1400,8 @@ static void setConfigs(opt::InputArgList &args) {
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// enable the debug checks for all targets, but currently not all targets
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// have support for reading Elf_Rel addends, so we only enable for a subset.
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#ifndef NDEBUG
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bool checkDynamicRelocsDefault =
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m == EM_ARM || m == EM_386 || m == EM_MIPS || m == EM_X86_64;
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bool checkDynamicRelocsDefault = m == EM_ARM || m == EM_386 || m == EM_MIPS ||
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m == EM_X86_64 || m == EM_RISCV;
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#else
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bool checkDynamicRelocsDefault = false;
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#endif
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