forked from OSchip/llvm-project
[PowerPC] Probe the gap between stackptr and realigned stackptr
During reviewing https://reviews.llvm.org/D84419, @efriedma mentioned the gap between realigned stack pointer and origin stack pointer should be probed too whatever the alignment is. This patch fixes the issue for PPC64. Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D88078
This commit is contained in:
Kai Luo
parent
1c82d32089
commit
97e7ce3b15
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@ -525,6 +525,8 @@ PPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB,
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// register is available, we can adjust for that by not overlapping the spill
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// code. However, if we need to realign the stack (i.e. have a base pointer)
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// and the stack frame is large, we need two scratch registers.
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// Also, stack probe requires two scratch registers, one for old sp, one for
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// large frame and large probe size.
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bool
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PPCFrameLowering::twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const {
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const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
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@ -536,8 +538,10 @@ PPCFrameLowering::twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const {
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MachineFrameInfo &MFI = MF.getFrameInfo();
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Align MaxAlign = MFI.getMaxAlign();
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bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI();
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const PPCTargetLowering &TLI = *Subtarget.getTargetLowering();
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return (IsLargeFrame || !HasRedZone) && HasBP && MaxAlign > 1;
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return ((IsLargeFrame || !HasRedZone) && HasBP && MaxAlign > 1) ||
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TLI.hasInlineStackProbe(MF);
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}
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bool PPCFrameLowering::canUseAsPrologue(const MachineBasicBlock &MBB) const {
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@ -676,12 +680,8 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
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"FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
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// Using the same bool variable as below to suppress compiler warnings.
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// Stack probe requires two scratch registers, one for old sp, one for large
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// frame and large probe size.
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bool SingleScratchReg = findScratchRegister(
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&MBB, false,
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twoUniqueScratchRegsRequired(&MBB) || TLI.hasInlineStackProbe(MF),
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&ScratchReg, &TempReg);
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&MBB, false, twoUniqueScratchRegsRequired(&MBB), &ScratchReg, &TempReg);
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assert(SingleScratchReg &&
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"Required number of registers not available in this block");
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@ -1202,10 +1202,12 @@ void PPCFrameLowering::inlineStackProbe(MachineFunction &MF,
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if (StackAllocMIPos == PrologMBB.end())
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return;
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const BasicBlock *ProbedBB = PrologMBB.getBasicBlock();
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MachineBasicBlock *CurrentMBB = &PrologMBB;
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DebugLoc DL = PrologMBB.findDebugLoc(StackAllocMIPos);
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MachineInstr &MI = *StackAllocMIPos;
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int64_t NegFrameSize = MI.getOperand(2).getImm();
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int64_t NegProbeSize = -(int64_t)TLI.getStackProbeSize(MF);
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unsigned ProbeSize = TLI.getStackProbeSize(MF);
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int64_t NegProbeSize = -(int64_t)ProbeSize;
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assert(isInt<32>(NegProbeSize) && "Unhandled probe size");
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int64_t NumBlocks = NegFrameSize / NegProbeSize;
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int64_t NegResidualSize = NegFrameSize % NegProbeSize;
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@ -1214,10 +1216,9 @@ void PPCFrameLowering::inlineStackProbe(MachineFunction &MF,
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Register FPReg = MI.getOperand(1).getReg();
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const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
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bool HasBP = RegInfo->hasBasePointer(MF);
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Register BPReg = RegInfo->getBaseRegister(MF);
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Align MaxAlign = MFI.getMaxAlign();
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// Initialize current frame pointer.
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const MCInstrDesc &CopyInst = TII.get(isPPC64 ? PPC::OR8 : PPC::OR);
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BuildMI(PrologMBB, {MI}, DL, CopyInst, FPReg).addReg(SPReg).addReg(SPReg);
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// Subroutines to generate .cfi_* directives.
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auto buildDefCFAReg = [&](MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, Register Reg) {
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@ -1257,89 +1258,218 @@ void PPCFrameLowering::inlineStackProbe(MachineFunction &MF,
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// Subroutine to store frame pointer and decrease stack pointer by probe size.
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auto allocateAndProbe = [&](MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, int64_t NegSize,
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Register NegSizeReg, bool UseDForm) {
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Register NegSizeReg, bool UseDForm,
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Register StoreReg) {
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if (UseDForm)
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BuildMI(MBB, MBBI, DL, TII.get(isPPC64 ? PPC::STDU : PPC::STWU), SPReg)
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.addReg(FPReg)
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.addReg(StoreReg)
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.addImm(NegSize)
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.addReg(SPReg);
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else
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BuildMI(MBB, MBBI, DL, TII.get(isPPC64 ? PPC::STDUX : PPC::STWUX), SPReg)
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.addReg(FPReg)
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.addReg(StoreReg)
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.addReg(SPReg)
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.addReg(NegSizeReg);
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};
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// Use FPReg to calculate CFA.
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if (needsCFI)
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buildDefCFA(PrologMBB, {MI}, FPReg, 0);
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// For case HasBP && MaxAlign > 1, we have to align the SP by performing
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// SP = SP - SP % MaxAlign.
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if (HasBP && MaxAlign > 1) {
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if (isPPC64)
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BuildMI(PrologMBB, {MI}, DL, TII.get(PPC::RLDICL), ScratchReg)
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.addReg(FPReg)
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// Used to probe realignment gap [stackptr - (stackptr % align), stackptr)
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// when HasBP && isPPC64. In such scenario, normally we have r0, r1, r12, r30
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// available and r1 is already copied to r30 which is BPReg. So BPReg stores
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// the value of stackptr.
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// First we have to probe tail interval whose size is less than probesize,
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// i.e., [stackptr - (stackptr % align) % probesize, stackptr). At this stage,
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// ScratchReg stores the value of ((stackptr % align) % probesize). Then we
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// probe each block sized probesize until stackptr meets
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// (stackptr - (stackptr % align)). At this stage, ScratchReg is materialized
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// as negprobesize. At both stages, TempReg stores the value of
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// (stackptr - (stackptr % align)).
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auto dynamicProbe = [&](MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, Register ScratchReg,
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Register TempReg) {
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assert(HasBP && isPPC64 && "Probe alignment part not available");
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assert(isPowerOf2_64(ProbeSize) && "Probe size should be power of 2");
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// ScratchReg = stackptr % align
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BuildMI(MBB, MBBI, DL, TII.get(PPC::RLDICL), ScratchReg)
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.addReg(BPReg)
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.addImm(0)
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.addImm(64 - Log2(MaxAlign));
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else
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BuildMI(PrologMBB, {MI}, DL, TII.get(PPC::RLWINM), ScratchReg)
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// TempReg = stackptr - (stackptr % align)
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BuildMI(MBB, MBBI, DL, TII.get(PPC::SUBFC8), TempReg)
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.addReg(ScratchReg)
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.addReg(BPReg);
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// ScratchReg = (stackptr % align) % probesize
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BuildMI(MBB, MBBI, DL, TII.get(PPC::RLDICL), ScratchReg)
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.addReg(ScratchReg)
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.addImm(0)
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.addImm(64 - Log2(ProbeSize));
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Register CRReg = PPC::CR0;
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// If (stackptr % align) % probesize == 0, we should not generate probe
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// code. Layout of output assembly kinda like:
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// bb.0:
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// ...
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// cmpldi $scratchreg, 0
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// beq bb.2
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// bb.1: # Probe tail interval
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// neg $scratchreg, $scratchreg
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// stdux $bpreg, r1, $scratchreg
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// bb.2:
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// <materialize negprobesize into $scratchreg>
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// cmpd r1, $tempreg
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// beq bb.4
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// bb.3: # Loop to probe each block
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// stdux $bpreg, r1, $scratchreg
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// cmpd r1, $tempreg
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// bne bb.3
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// bb.4:
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// ...
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MachineFunction::iterator MBBInsertPoint = std::next(MBB.getIterator());
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MachineBasicBlock *ProbeResidualMBB = MF.CreateMachineBasicBlock(ProbedBB);
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MF.insert(MBBInsertPoint, ProbeResidualMBB);
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MachineBasicBlock *ProbeLoopPreHeaderMBB =
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MF.CreateMachineBasicBlock(ProbedBB);
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MF.insert(MBBInsertPoint, ProbeLoopPreHeaderMBB);
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MachineBasicBlock *ProbeLoopBodyMBB = MF.CreateMachineBasicBlock(ProbedBB);
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MF.insert(MBBInsertPoint, ProbeLoopBodyMBB);
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MachineBasicBlock *ProbeExitMBB = MF.CreateMachineBasicBlock(ProbedBB);
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MF.insert(MBBInsertPoint, ProbeExitMBB);
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// bb.4
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ProbeExitMBB->splice(ProbeExitMBB->end(), &MBB, MBBI, MBB.end());
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ProbeExitMBB->transferSuccessorsAndUpdatePHIs(&MBB);
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// bb.0
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BuildMI(&MBB, DL, TII.get(PPC::CMPDI), CRReg).addReg(ScratchReg).addImm(0);
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BuildMI(&MBB, DL, TII.get(PPC::BCC))
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.addImm(PPC::PRED_EQ)
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.addReg(CRReg)
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.addMBB(ProbeLoopPreHeaderMBB);
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MBB.addSuccessor(ProbeResidualMBB);
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MBB.addSuccessor(ProbeLoopPreHeaderMBB);
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// bb.1
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BuildMI(ProbeResidualMBB, DL, TII.get(PPC::NEG8), ScratchReg)
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.addReg(ScratchReg);
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allocateAndProbe(*ProbeResidualMBB, ProbeResidualMBB->end(), 0, ScratchReg,
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false, BPReg);
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ProbeResidualMBB->addSuccessor(ProbeLoopPreHeaderMBB);
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// bb.2
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MaterializeImm(*ProbeLoopPreHeaderMBB, ProbeLoopPreHeaderMBB->end(),
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NegProbeSize, ScratchReg);
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BuildMI(ProbeLoopPreHeaderMBB, DL, TII.get(PPC::CMPD), CRReg)
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.addReg(SPReg)
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.addReg(TempReg);
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BuildMI(ProbeLoopPreHeaderMBB, DL, TII.get(PPC::BCC))
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.addImm(PPC::PRED_EQ)
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.addReg(CRReg)
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.addMBB(ProbeExitMBB);
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ProbeLoopPreHeaderMBB->addSuccessor(ProbeLoopBodyMBB);
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ProbeLoopPreHeaderMBB->addSuccessor(ProbeExitMBB);
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// bb.3
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allocateAndProbe(*ProbeLoopBodyMBB, ProbeLoopBodyMBB->end(), 0, ScratchReg,
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false, BPReg);
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BuildMI(ProbeLoopBodyMBB, DL, TII.get(PPC::CMPD), CRReg)
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.addReg(SPReg)
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.addReg(TempReg);
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BuildMI(ProbeLoopBodyMBB, DL, TII.get(PPC::BCC))
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.addImm(PPC::PRED_NE)
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.addReg(CRReg)
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.addMBB(ProbeLoopBodyMBB);
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ProbeLoopBodyMBB->addSuccessor(ProbeExitMBB);
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ProbeLoopBodyMBB->addSuccessor(ProbeLoopBodyMBB);
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// Update liveins.
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recomputeLiveIns(*ProbeResidualMBB);
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recomputeLiveIns(*ProbeLoopPreHeaderMBB);
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recomputeLiveIns(*ProbeLoopBodyMBB);
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recomputeLiveIns(*ProbeExitMBB);
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return ProbeExitMBB;
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};
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// For case HasBP && MaxAlign > 1, we have to realign the SP by performing
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// SP = SP - SP % MaxAlign.
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if (HasBP && MaxAlign > 1) {
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// FIXME: Currently only probe the gap [stackptr & alignmask, stackptr) in
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// 64-bit mode.
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if (isPPC64) {
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// Use BPReg to calculate CFA.
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if (needsCFI)
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buildDefCFA(*CurrentMBB, {MI}, BPReg, 0);
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// Since we have SPReg copied to BPReg at the moment, FPReg can be used as
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// TempReg.
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Register TempReg = FPReg;
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CurrentMBB = dynamicProbe(*CurrentMBB, {MI}, ScratchReg, TempReg);
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// Copy BPReg to FPReg to meet the definition of PROBED_STACKALLOC_64.
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BuildMI(*CurrentMBB, {MI}, DL, CopyInst, FPReg)
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.addReg(BPReg)
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.addReg(BPReg);
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} else {
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// Initialize current frame pointer.
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BuildMI(*CurrentMBB, {MI}, DL, CopyInst, FPReg)
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.addReg(SPReg)
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.addReg(SPReg);
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// Use FPReg to calculate CFA.
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if (needsCFI)
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buildDefCFA(*CurrentMBB, {MI}, FPReg, 0);
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BuildMI(*CurrentMBB, {MI}, DL, TII.get(PPC::RLWINM), ScratchReg)
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.addReg(FPReg)
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.addImm(0)
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.addImm(32 - Log2(MaxAlign))
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.addImm(31);
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BuildMI(PrologMBB, {MI}, DL, TII.get(isPPC64 ? PPC::SUBFC8 : PPC::SUBFC),
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SPReg)
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BuildMI(*CurrentMBB, {MI}, DL, TII.get(PPC::SUBFC), SPReg)
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.addReg(ScratchReg)
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.addReg(SPReg);
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}
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} else {
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// Initialize current frame pointer.
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BuildMI(*CurrentMBB, {MI}, DL, CopyInst, FPReg).addReg(SPReg).addReg(SPReg);
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// Use FPReg to calculate CFA.
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if (needsCFI)
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buildDefCFA(*CurrentMBB, {MI}, FPReg, 0);
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}
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// Probe residual part.
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if (NegResidualSize) {
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bool ResidualUseDForm = CanUseDForm(NegResidualSize);
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if (!ResidualUseDForm)
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MaterializeImm(PrologMBB, {MI}, NegResidualSize, ScratchReg);
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allocateAndProbe(PrologMBB, {MI}, NegResidualSize, ScratchReg,
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ResidualUseDForm);
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MaterializeImm(*CurrentMBB, {MI}, NegResidualSize, ScratchReg);
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allocateAndProbe(*CurrentMBB, {MI}, NegResidualSize, ScratchReg,
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ResidualUseDForm, FPReg);
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}
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bool UseDForm = CanUseDForm(NegProbeSize);
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// If number of blocks is small, just probe them directly.
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if (NumBlocks < 3) {
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if (!UseDForm)
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MaterializeImm(PrologMBB, {MI}, NegProbeSize, ScratchReg);
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MaterializeImm(*CurrentMBB, {MI}, NegProbeSize, ScratchReg);
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for (int i = 0; i < NumBlocks; ++i)
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allocateAndProbe(PrologMBB, {MI}, NegProbeSize, ScratchReg, UseDForm);
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allocateAndProbe(*CurrentMBB, {MI}, NegProbeSize, ScratchReg, UseDForm,
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FPReg);
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if (needsCFI) {
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// Restore using SPReg to calculate CFA.
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buildDefCFAReg(PrologMBB, {MI}, SPReg);
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buildDefCFAReg(*CurrentMBB, {MI}, SPReg);
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}
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} else {
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// Since CTR is a volatile register and current shrinkwrap implementation
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// won't choose an MBB in a loop as the PrologMBB, it's safe to synthesize a
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// CTR loop to probe.
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// Calculate trip count and stores it in CTRReg.
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MaterializeImm(PrologMBB, {MI}, NumBlocks, ScratchReg);
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BuildMI(PrologMBB, {MI}, DL, TII.get(isPPC64 ? PPC::MTCTR8 : PPC::MTCTR))
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MaterializeImm(*CurrentMBB, {MI}, NumBlocks, ScratchReg);
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BuildMI(*CurrentMBB, {MI}, DL, TII.get(isPPC64 ? PPC::MTCTR8 : PPC::MTCTR))
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.addReg(ScratchReg, RegState::Kill);
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if (!UseDForm)
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MaterializeImm(PrologMBB, {MI}, NegProbeSize, ScratchReg);
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MaterializeImm(*CurrentMBB, {MI}, NegProbeSize, ScratchReg);
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// Create MBBs of the loop.
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MachineFunction::iterator MBBInsertPoint =
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std::next(PrologMBB.getIterator());
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std::next(CurrentMBB->getIterator());
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MachineBasicBlock *LoopMBB = MF.CreateMachineBasicBlock(ProbedBB);
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MF.insert(MBBInsertPoint, LoopMBB);
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MachineBasicBlock *ExitMBB = MF.CreateMachineBasicBlock(ProbedBB);
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MF.insert(MBBInsertPoint, ExitMBB);
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// Synthesize the loop body.
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allocateAndProbe(*LoopMBB, LoopMBB->end(), NegProbeSize, ScratchReg,
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UseDForm);
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UseDForm, FPReg);
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BuildMI(LoopMBB, DL, TII.get(isPPC64 ? PPC::BDNZ8 : PPC::BDNZ))
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.addMBB(LoopMBB);
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LoopMBB->addSuccessor(ExitMBB);
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LoopMBB->addSuccessor(LoopMBB);
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// Synthesize the exit MBB.
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ExitMBB->splice(ExitMBB->end(), &PrologMBB,
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ExitMBB->splice(ExitMBB->end(), CurrentMBB,
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std::next(MachineBasicBlock::iterator(MI)),
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PrologMBB.end());
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ExitMBB->transferSuccessorsAndUpdatePHIs(&PrologMBB);
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PrologMBB.addSuccessor(LoopMBB);
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CurrentMBB->end());
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ExitMBB->transferSuccessorsAndUpdatePHIs(CurrentMBB);
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CurrentMBB->addSuccessor(LoopMBB);
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if (needsCFI) {
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// Restore using SPReg to calculate CFA.
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buildDefCFAReg(*ExitMBB, ExitMBB->begin(), SPReg);
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@ -9,10 +9,26 @@ define void @foo(i32 %vla_size) #0 {
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; CHECK-LE-NEXT: std r31, -8(r1)
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; CHECK-LE-NEXT: std r30, -16(r1)
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; CHECK-LE-NEXT: mr r30, r1
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; CHECK-LE-NEXT: mr r12, r1
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; CHECK-LE-NEXT: .cfi_def_cfa r12, 0
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; CHECK-LE-NEXT: clrldi r0, r12, 53
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; CHECK-LE-NEXT: subc r1, r1, r0
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; CHECK-LE-NEXT: .cfi_def_cfa r30, 0
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; CHECK-LE-NEXT: clrldi r0, r30, 53
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; CHECK-LE-NEXT: subc r12, r30, r0
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; CHECK-LE-NEXT: clrldi r0, r0, 52
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; CHECK-LE-NEXT: cmpdi r0, 0
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; CHECK-LE-NEXT: beq cr0, .LBB0_2
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; CHECK-LE-NEXT: # %bb.1: # %entry
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; CHECK-LE-NEXT: neg r0, r0
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; CHECK-LE-NEXT: stdux r30, r1, r0
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; CHECK-LE-NEXT: .LBB0_2: # %entry
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; CHECK-LE-NEXT: li r0, -4096
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; CHECK-LE-NEXT: cmpd r1, r12
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; CHECK-LE-NEXT: beq cr0, .LBB0_4
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; CHECK-LE-NEXT: .LBB0_3: # %entry
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; CHECK-LE-NEXT: #
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; CHECK-LE-NEXT: stdux r30, r1, r0
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; CHECK-LE-NEXT: cmpd r1, r12
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; CHECK-LE-NEXT: bne cr0, .LBB0_3
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; CHECK-LE-NEXT: .LBB0_4: # %entry
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; CHECK-LE-NEXT: mr r12, r30
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; CHECK-LE-NEXT: stdu r12, -2048(r1)
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; CHECK-LE-NEXT: stdu r12, -4096(r1)
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; CHECK-LE-NEXT: .cfi_def_cfa_register r1
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@ -36,13 +52,13 @@ define void @foo(i32 %vla_size) #0 {
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|||
; CHECK-LE-NEXT: add r4, r1, r4
|
||||
; CHECK-LE-NEXT: stdux r3, r1, r5
|
||||
; CHECK-LE-NEXT: cmpd r1, r4
|
||||
; CHECK-LE-NEXT: beq cr0, .LBB0_2
|
||||
; CHECK-LE-NEXT: .LBB0_1: # %entry
|
||||
; CHECK-LE-NEXT: beq cr0, .LBB0_6
|
||||
; CHECK-LE-NEXT: .LBB0_5: # %entry
|
||||
; CHECK-LE-NEXT: #
|
||||
; CHECK-LE-NEXT: stdu r3, -4096(r1)
|
||||
; CHECK-LE-NEXT: cmpd r1, r4
|
||||
; CHECK-LE-NEXT: bne cr0, .LBB0_1
|
||||
; CHECK-LE-NEXT: .LBB0_2: # %entry
|
||||
; CHECK-LE-NEXT: bne cr0, .LBB0_5
|
||||
; CHECK-LE-NEXT: .LBB0_6: # %entry
|
||||
; CHECK-LE-NEXT: addi r3, r1, 2048
|
||||
; CHECK-LE-NEXT: lbz r3, 0(r3)
|
||||
; CHECK-LE-NEXT: ld r1, 0(r1)
|
||||
|
|
|
|||
|
|
@ -528,4 +528,502 @@ entry:
|
|||
ret i8 %c
|
||||
}
|
||||
|
||||
; alloca + align < probe_size
|
||||
define i32 @f8(i64 %i) local_unnamed_addr #0 {
|
||||
; CHECK-LE-LABEL: f8:
|
||||
; CHECK-LE: # %bb.0:
|
||||
; CHECK-LE-NEXT: clrldi r0, r1, 58
|
||||
; CHECK-LE-NEXT: std r30, -16(r1)
|
||||
; CHECK-LE-NEXT: mr r30, r1
|
||||
; CHECK-LE-NEXT: subfic r0, r0, -896
|
||||
; CHECK-LE-NEXT: stdux r1, r1, r0
|
||||
; CHECK-LE-NEXT: .cfi_def_cfa_register r30
|
||||
; CHECK-LE-NEXT: .cfi_offset r30, -16
|
||||
; CHECK-LE-NEXT: addi r4, r1, 64
|
||||
; CHECK-LE-NEXT: sldi r3, r3, 2
|
||||
; CHECK-LE-NEXT: li r5, 1
|
||||
; CHECK-LE-NEXT: stwx r5, r4, r3
|
||||
; CHECK-LE-NEXT: lwz r3, 64(r1)
|
||||
; CHECK-LE-NEXT: ld r1, 0(r1)
|
||||
; CHECK-LE-NEXT: ld r30, -16(r1)
|
||||
; CHECK-LE-NEXT: blr
|
||||
;
|
||||
; CHECK-BE-LABEL: f8:
|
||||
; CHECK-BE: # %bb.0:
|
||||
; CHECK-BE-NEXT: clrldi r0, r1, 58
|
||||
; CHECK-BE-NEXT: std r30, -16(r1)
|
||||
; CHECK-BE-NEXT: mr r30, r1
|
||||
; CHECK-BE-NEXT: subfic r0, r0, -896
|
||||
; CHECK-BE-NEXT: stdux r1, r1, r0
|
||||
; CHECK-BE-NEXT: .cfi_def_cfa_register r30
|
||||
; CHECK-BE-NEXT: .cfi_offset r30, -16
|
||||
; CHECK-BE-NEXT: addi r4, r1, 64
|
||||
; CHECK-BE-NEXT: li r5, 1
|
||||
; CHECK-BE-NEXT: sldi r3, r3, 2
|
||||
; CHECK-BE-NEXT: stwx r5, r4, r3
|
||||
; CHECK-BE-NEXT: lwz r3, 64(r1)
|
||||
; CHECK-BE-NEXT: ld r1, 0(r1)
|
||||
; CHECK-BE-NEXT: ld r30, -16(r1)
|
||||
; CHECK-BE-NEXT: blr
|
||||
;
|
||||
; CHECK-32-LABEL: f8:
|
||||
; CHECK-32: # %bb.0:
|
||||
; CHECK-32-NEXT: clrlwi r0, r1, 26
|
||||
; CHECK-32-NEXT: subfic r0, r0, -896
|
||||
; CHECK-32-NEXT: stwux r1, r1, r0
|
||||
; CHECK-32-NEXT: sub r0, r1, r0
|
||||
; CHECK-32-NEXT: addic r0, r0, -8
|
||||
; CHECK-32-NEXT: stwx r30, 0, r0
|
||||
; CHECK-32-NEXT: addic r30, r0, 8
|
||||
; CHECK-32-NEXT: .cfi_def_cfa_register r30
|
||||
; CHECK-32-NEXT: .cfi_offset r30, -8
|
||||
; CHECK-32-NEXT: addi r3, r1, 64
|
||||
; CHECK-32-NEXT: li r5, 1
|
||||
; CHECK-32-NEXT: slwi r4, r4, 2
|
||||
; CHECK-32-NEXT: stwx r5, r3, r4
|
||||
; CHECK-32-NEXT: mr r0, r31
|
||||
; CHECK-32-NEXT: lwz r3, 64(r1)
|
||||
; CHECK-32-NEXT: lwz r31, 0(r1)
|
||||
; CHECK-32-NEXT: lwz r30, -8(r31)
|
||||
; CHECK-32-NEXT: mr r1, r31
|
||||
; CHECK-32-NEXT: mr r31, r0
|
||||
; CHECK-32-NEXT: blr
|
||||
%a = alloca i32, i32 200, align 64
|
||||
%b = getelementptr inbounds i32, i32* %a, i64 %i
|
||||
store volatile i32 1, i32* %b
|
||||
%c = load volatile i32, i32* %a
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
; alloca > probe_size, align > probe_size
|
||||
define i32 @f9(i64 %i) local_unnamed_addr #0 {
|
||||
; CHECK-LE-LABEL: f9:
|
||||
; CHECK-LE: # %bb.0:
|
||||
; CHECK-LE-NEXT: std r30, -16(r1)
|
||||
; CHECK-LE-NEXT: mr r30, r1
|
||||
; CHECK-LE-NEXT: .cfi_def_cfa r30, 0
|
||||
; CHECK-LE-NEXT: clrldi r0, r30, 53
|
||||
; CHECK-LE-NEXT: subc r12, r30, r0
|
||||
; CHECK-LE-NEXT: clrldi r0, r0, 52
|
||||
; CHECK-LE-NEXT: cmpdi r0, 0
|
||||
; CHECK-LE-NEXT: beq cr0, .LBB9_2
|
||||
; CHECK-LE-NEXT: # %bb.1:
|
||||
; CHECK-LE-NEXT: neg r0, r0
|
||||
; CHECK-LE-NEXT: stdux r30, r1, r0
|
||||
; CHECK-LE-NEXT: .LBB9_2:
|
||||
; CHECK-LE-NEXT: li r0, -4096
|
||||
; CHECK-LE-NEXT: cmpd r1, r12
|
||||
; CHECK-LE-NEXT: beq cr0, .LBB9_4
|
||||
; CHECK-LE-NEXT: .LBB9_3:
|
||||
; CHECK-LE-NEXT: stdux r30, r1, r0
|
||||
; CHECK-LE-NEXT: cmpd r1, r12
|
||||
; CHECK-LE-NEXT: bne cr0, .LBB9_3
|
||||
; CHECK-LE-NEXT: .LBB9_4:
|
||||
; CHECK-LE-NEXT: mr r12, r30
|
||||
; CHECK-LE-NEXT: stdu r12, -2048(r1)
|
||||
; CHECK-LE-NEXT: stdu r12, -4096(r1)
|
||||
; CHECK-LE-NEXT: stdu r12, -4096(r1)
|
||||
; CHECK-LE-NEXT: .cfi_def_cfa_register r1
|
||||
; CHECK-LE-NEXT: .cfi_def_cfa_register r30
|
||||
; CHECK-LE-NEXT: .cfi_offset r30, -16
|
||||
; CHECK-LE-NEXT: addi r4, r1, 2048
|
||||
; CHECK-LE-NEXT: sldi r3, r3, 2
|
||||
; CHECK-LE-NEXT: li r5, 1
|
||||
; CHECK-LE-NEXT: stwx r5, r4, r3
|
||||
; CHECK-LE-NEXT: lwz r3, 2048(r1)
|
||||
; CHECK-LE-NEXT: ld r1, 0(r1)
|
||||
; CHECK-LE-NEXT: ld r30, -16(r1)
|
||||
; CHECK-LE-NEXT: blr
|
||||
;
|
||||
; CHECK-BE-LABEL: f9:
|
||||
; CHECK-BE: # %bb.0:
|
||||
; CHECK-BE-NEXT: std r30, -16(r1)
|
||||
; CHECK-BE-NEXT: mr r30, r1
|
||||
; CHECK-BE-NEXT: .cfi_def_cfa r30, 0
|
||||
; CHECK-BE-NEXT: clrldi r0, r30, 53
|
||||
; CHECK-BE-NEXT: subc r12, r30, r0
|
||||
; CHECK-BE-NEXT: clrldi r0, r0, 52
|
||||
; CHECK-BE-NEXT: cmpdi r0, 0
|
||||
; CHECK-BE-NEXT: beq cr0, .LBB9_2
|
||||
; CHECK-BE-NEXT: # %bb.1:
|
||||
; CHECK-BE-NEXT: neg r0, r0
|
||||
; CHECK-BE-NEXT: stdux r30, r1, r0
|
||||
; CHECK-BE-NEXT: .LBB9_2:
|
||||
; CHECK-BE-NEXT: li r0, -4096
|
||||
; CHECK-BE-NEXT: cmpd r1, r12
|
||||
; CHECK-BE-NEXT: beq cr0, .LBB9_4
|
||||
; CHECK-BE-NEXT: .LBB9_3:
|
||||
; CHECK-BE-NEXT: stdux r30, r1, r0
|
||||
; CHECK-BE-NEXT: cmpd r1, r12
|
||||
; CHECK-BE-NEXT: bne cr0, .LBB9_3
|
||||
; CHECK-BE-NEXT: .LBB9_4:
|
||||
; CHECK-BE-NEXT: mr r12, r30
|
||||
; CHECK-BE-NEXT: stdu r12, -2048(r1)
|
||||
; CHECK-BE-NEXT: stdu r12, -4096(r1)
|
||||
; CHECK-BE-NEXT: stdu r12, -4096(r1)
|
||||
; CHECK-BE-NEXT: .cfi_def_cfa_register r1
|
||||
; CHECK-BE-NEXT: .cfi_def_cfa_register r30
|
||||
; CHECK-BE-NEXT: .cfi_offset r30, -16
|
||||
; CHECK-BE-NEXT: addi r4, r1, 2048
|
||||
; CHECK-BE-NEXT: li r5, 1
|
||||
; CHECK-BE-NEXT: sldi r3, r3, 2
|
||||
; CHECK-BE-NEXT: stwx r5, r4, r3
|
||||
; CHECK-BE-NEXT: lwz r3, 2048(r1)
|
||||
; CHECK-BE-NEXT: ld r1, 0(r1)
|
||||
; CHECK-BE-NEXT: ld r30, -16(r1)
|
||||
; CHECK-BE-NEXT: blr
|
||||
;
|
||||
; CHECK-32-LABEL: f9:
|
||||
; CHECK-32: # %bb.0:
|
||||
; CHECK-32-NEXT: mr r12, r1
|
||||
; CHECK-32-NEXT: .cfi_def_cfa r12, 0
|
||||
; CHECK-32-NEXT: clrlwi r0, r12, 21
|
||||
; CHECK-32-NEXT: subc r1, r1, r0
|
||||
; CHECK-32-NEXT: stwu r12, -2048(r1)
|
||||
; CHECK-32-NEXT: stwu r12, -4096(r1)
|
||||
; CHECK-32-NEXT: stwu r12, -4096(r1)
|
||||
; CHECK-32-NEXT: .cfi_def_cfa_register r1
|
||||
; CHECK-32-NEXT: sub r0, r1, r12
|
||||
; CHECK-32-NEXT: sub r0, r1, r0
|
||||
; CHECK-32-NEXT: addic r0, r0, -8
|
||||
; CHECK-32-NEXT: stwx r30, 0, r0
|
||||
; CHECK-32-NEXT: addic r30, r0, 8
|
||||
; CHECK-32-NEXT: .cfi_def_cfa_register r30
|
||||
; CHECK-32-NEXT: .cfi_offset r30, -8
|
||||
; CHECK-32-NEXT: addi r3, r1, 2048
|
||||
; CHECK-32-NEXT: li r5, 1
|
||||
; CHECK-32-NEXT: slwi r4, r4, 2
|
||||
; CHECK-32-NEXT: stwx r5, r3, r4
|
||||
; CHECK-32-NEXT: mr r0, r31
|
||||
; CHECK-32-NEXT: lwz r3, 2048(r1)
|
||||
; CHECK-32-NEXT: lwz r31, 0(r1)
|
||||
; CHECK-32-NEXT: lwz r30, -8(r31)
|
||||
; CHECK-32-NEXT: mr r1, r31
|
||||
; CHECK-32-NEXT: mr r31, r0
|
||||
; CHECK-32-NEXT: blr
|
||||
%a = alloca i32, i32 2000, align 2048
|
||||
%b = getelementptr inbounds i32, i32* %a, i64 %i
|
||||
store volatile i32 1, i32* %b
|
||||
%c = load volatile i32, i32* %a
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
; alloca < probe_size, align < probe_size, alloca + align > probe_size
|
||||
define i32 @f10(i64 %i) local_unnamed_addr #0 {
|
||||
; CHECK-LE-LABEL: f10:
|
||||
; CHECK-LE: # %bb.0:
|
||||
; CHECK-LE-NEXT: std r30, -16(r1)
|
||||
; CHECK-LE-NEXT: mr r30, r1
|
||||
; CHECK-LE-NEXT: .cfi_def_cfa r30, 0
|
||||
; CHECK-LE-NEXT: clrldi r0, r30, 54
|
||||
; CHECK-LE-NEXT: subc r12, r30, r0
|
||||
; CHECK-LE-NEXT: clrldi r0, r0, 52
|
||||
; CHECK-LE-NEXT: cmpdi r0, 0
|
||||
; CHECK-LE-NEXT: beq cr0, .LBB10_2
|
||||
; CHECK-LE-NEXT: # %bb.1:
|
||||
; CHECK-LE-NEXT: neg r0, r0
|
||||
; CHECK-LE-NEXT: stdux r30, r1, r0
|
||||
; CHECK-LE-NEXT: .LBB10_2:
|
||||
; CHECK-LE-NEXT: li r0, -4096
|
||||
; CHECK-LE-NEXT: cmpd r1, r12
|
||||
; CHECK-LE-NEXT: beq cr0, .LBB10_4
|
||||
; CHECK-LE-NEXT: .LBB10_3:
|
||||
; CHECK-LE-NEXT: stdux r30, r1, r0
|
||||
; CHECK-LE-NEXT: cmpd r1, r12
|
||||
; CHECK-LE-NEXT: bne cr0, .LBB10_3
|
||||
; CHECK-LE-NEXT: .LBB10_4:
|
||||
; CHECK-LE-NEXT: mr r12, r30
|
||||
; CHECK-LE-NEXT: stdu r12, -1024(r1)
|
||||
; CHECK-LE-NEXT: stdu r12, -4096(r1)
|
||||
; CHECK-LE-NEXT: .cfi_def_cfa_register r1
|
||||
; CHECK-LE-NEXT: .cfi_def_cfa_register r30
|
||||
; CHECK-LE-NEXT: .cfi_offset r30, -16
|
||||
; CHECK-LE-NEXT: addi r4, r1, 1024
|
||||
; CHECK-LE-NEXT: sldi r3, r3, 2
|
||||
; CHECK-LE-NEXT: li r5, 1
|
||||
; CHECK-LE-NEXT: stwx r5, r4, r3
|
||||
; CHECK-LE-NEXT: lwz r3, 1024(r1)
|
||||
; CHECK-LE-NEXT: ld r1, 0(r1)
|
||||
; CHECK-LE-NEXT: ld r30, -16(r1)
|
||||
; CHECK-LE-NEXT: blr
|
||||
;
|
||||
; CHECK-BE-LABEL: f10:
|
||||
; CHECK-BE: # %bb.0:
|
||||
; CHECK-BE-NEXT: std r30, -16(r1)
|
||||
; CHECK-BE-NEXT: mr r30, r1
|
||||
; CHECK-BE-NEXT: .cfi_def_cfa r30, 0
|
||||
; CHECK-BE-NEXT: clrldi r0, r30, 54
|
||||
; CHECK-BE-NEXT: subc r12, r30, r0
|
||||
; CHECK-BE-NEXT: clrldi r0, r0, 52
|
||||
; CHECK-BE-NEXT: cmpdi r0, 0
|
||||
; CHECK-BE-NEXT: beq cr0, .LBB10_2
|
||||
; CHECK-BE-NEXT: # %bb.1:
|
||||
; CHECK-BE-NEXT: neg r0, r0
|
||||
; CHECK-BE-NEXT: stdux r30, r1, r0
|
||||
; CHECK-BE-NEXT: .LBB10_2:
|
||||
; CHECK-BE-NEXT: li r0, -4096
|
||||
; CHECK-BE-NEXT: cmpd r1, r12
|
||||
; CHECK-BE-NEXT: beq cr0, .LBB10_4
|
||||
; CHECK-BE-NEXT: .LBB10_3:
|
||||
; CHECK-BE-NEXT: stdux r30, r1, r0
|
||||
; CHECK-BE-NEXT: cmpd r1, r12
|
||||
; CHECK-BE-NEXT: bne cr0, .LBB10_3
|
||||
; CHECK-BE-NEXT: .LBB10_4:
|
||||
; CHECK-BE-NEXT: mr r12, r30
|
||||
; CHECK-BE-NEXT: stdu r12, -1024(r1)
|
||||
; CHECK-BE-NEXT: stdu r12, -4096(r1)
|
||||
; CHECK-BE-NEXT: .cfi_def_cfa_register r1
|
||||
; CHECK-BE-NEXT: .cfi_def_cfa_register r30
|
||||
; CHECK-BE-NEXT: .cfi_offset r30, -16
|
||||
; CHECK-BE-NEXT: addi r4, r1, 1024
|
||||
; CHECK-BE-NEXT: li r5, 1
|
||||
; CHECK-BE-NEXT: sldi r3, r3, 2
|
||||
; CHECK-BE-NEXT: stwx r5, r4, r3
|
||||
; CHECK-BE-NEXT: lwz r3, 1024(r1)
|
||||
; CHECK-BE-NEXT: ld r1, 0(r1)
|
||||
; CHECK-BE-NEXT: ld r30, -16(r1)
|
||||
; CHECK-BE-NEXT: blr
|
||||
;
|
||||
; CHECK-32-LABEL: f10:
|
||||
; CHECK-32: # %bb.0:
|
||||
; CHECK-32-NEXT: mr r12, r1
|
||||
; CHECK-32-NEXT: .cfi_def_cfa r12, 0
|
||||
; CHECK-32-NEXT: clrlwi r0, r12, 22
|
||||
; CHECK-32-NEXT: subc r1, r1, r0
|
||||
; CHECK-32-NEXT: stwu r12, -1024(r1)
|
||||
; CHECK-32-NEXT: stwu r12, -4096(r1)
|
||||
; CHECK-32-NEXT: .cfi_def_cfa_register r1
|
||||
; CHECK-32-NEXT: sub r0, r1, r12
|
||||
; CHECK-32-NEXT: sub r0, r1, r0
|
||||
; CHECK-32-NEXT: addic r0, r0, -8
|
||||
; CHECK-32-NEXT: stwx r30, 0, r0
|
||||
; CHECK-32-NEXT: addic r30, r0, 8
|
||||
; CHECK-32-NEXT: .cfi_def_cfa_register r30
|
||||
; CHECK-32-NEXT: .cfi_offset r30, -8
|
||||
; CHECK-32-NEXT: addi r3, r1, 1024
|
||||
; CHECK-32-NEXT: li r5, 1
|
||||
; CHECK-32-NEXT: slwi r4, r4, 2
|
||||
; CHECK-32-NEXT: stwx r5, r3, r4
|
||||
; CHECK-32-NEXT: mr r0, r31
|
||||
; CHECK-32-NEXT: lwz r3, 1024(r1)
|
||||
; CHECK-32-NEXT: lwz r31, 0(r1)
|
||||
; CHECK-32-NEXT: lwz r30, -8(r31)
|
||||
; CHECK-32-NEXT: mr r1, r31
|
||||
; CHECK-32-NEXT: mr r31, r0
|
||||
; CHECK-32-NEXT: blr
|
||||
%a = alloca i32, i32 1000, align 1024
|
||||
%b = getelementptr inbounds i32, i32* %a, i64 %i
|
||||
store volatile i32 1, i32* %b
|
||||
%c = load volatile i32, i32* %a
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define void @f11(i32 %vla_size, i64 %i) #0 {
|
||||
; CHECK-LE-LABEL: f11:
|
||||
; CHECK-LE: # %bb.0:
|
||||
; CHECK-LE-NEXT: std r31, -8(r1)
|
||||
; CHECK-LE-NEXT: std r30, -16(r1)
|
||||
; CHECK-LE-NEXT: mr r30, r1
|
||||
; CHECK-LE-NEXT: .cfi_def_cfa r30, 0
|
||||
; CHECK-LE-NEXT: clrldi r0, r30, 49
|
||||
; CHECK-LE-NEXT: subc r12, r30, r0
|
||||
; CHECK-LE-NEXT: clrldi r0, r0, 52
|
||||
; CHECK-LE-NEXT: cmpdi r0, 0
|
||||
; CHECK-LE-NEXT: beq cr0, .LBB11_2
|
||||
; CHECK-LE-NEXT: # %bb.1:
|
||||
; CHECK-LE-NEXT: neg r0, r0
|
||||
; CHECK-LE-NEXT: stdux r30, r1, r0
|
||||
; CHECK-LE-NEXT: .LBB11_2:
|
||||
; CHECK-LE-NEXT: li r0, -4096
|
||||
; CHECK-LE-NEXT: cmpd r1, r12
|
||||
; CHECK-LE-NEXT: beq cr0, .LBB11_4
|
||||
; CHECK-LE-NEXT: .LBB11_3:
|
||||
; CHECK-LE-NEXT: stdux r30, r1, r0
|
||||
; CHECK-LE-NEXT: cmpd r1, r12
|
||||
; CHECK-LE-NEXT: bne cr0, .LBB11_3
|
||||
; CHECK-LE-NEXT: .LBB11_4:
|
||||
; CHECK-LE-NEXT: mr r12, r30
|
||||
; CHECK-LE-NEXT: li r0, 24
|
||||
; CHECK-LE-NEXT: mtctr r0
|
||||
; CHECK-LE-NEXT: .LBB11_5:
|
||||
; CHECK-LE-NEXT: stdu r12, -4096(r1)
|
||||
; CHECK-LE-NEXT: bdnz .LBB11_5
|
||||
; CHECK-LE-NEXT: # %bb.6:
|
||||
; CHECK-LE-NEXT: .cfi_def_cfa_register r1
|
||||
; CHECK-LE-NEXT: .cfi_def_cfa_register r30
|
||||
; CHECK-LE-NEXT: .cfi_offset r31, -8
|
||||
; CHECK-LE-NEXT: .cfi_offset r30, -16
|
||||
; CHECK-LE-NEXT: clrldi r3, r3, 32
|
||||
; CHECK-LE-NEXT: lis r5, 1
|
||||
; CHECK-LE-NEXT: mr r31, r1
|
||||
; CHECK-LE-NEXT: li r6, 1
|
||||
; CHECK-LE-NEXT: addi r3, r3, 15
|
||||
; CHECK-LE-NEXT: ori r5, r5, 0
|
||||
; CHECK-LE-NEXT: rldicl r3, r3, 60, 4
|
||||
; CHECK-LE-NEXT: sldi r4, r4, 2
|
||||
; CHECK-LE-NEXT: add r5, r31, r5
|
||||
; CHECK-LE-NEXT: rldicl r3, r3, 4, 31
|
||||
; CHECK-LE-NEXT: stwx r6, r5, r4
|
||||
; CHECK-LE-NEXT: li r4, -32768
|
||||
; CHECK-LE-NEXT: neg r7, r3
|
||||
; CHECK-LE-NEXT: ld r3, 0(r1)
|
||||
; CHECK-LE-NEXT: and r4, r7, r4
|
||||
; CHECK-LE-NEXT: mr r7, r4
|
||||
; CHECK-LE-NEXT: li r4, -4096
|
||||
; CHECK-LE-NEXT: divd r5, r7, r4
|
||||
; CHECK-LE-NEXT: mulld r4, r5, r4
|
||||
; CHECK-LE-NEXT: sub r5, r7, r4
|
||||
; CHECK-LE-NEXT: add r4, r1, r7
|
||||
; CHECK-LE-NEXT: stdux r3, r1, r5
|
||||
; CHECK-LE-NEXT: cmpd r1, r4
|
||||
; CHECK-LE-NEXT: beq cr0, .LBB11_8
|
||||
; CHECK-LE-NEXT: .LBB11_7:
|
||||
; CHECK-LE-NEXT: stdu r3, -4096(r1)
|
||||
; CHECK-LE-NEXT: cmpd r1, r4
|
||||
; CHECK-LE-NEXT: bne cr0, .LBB11_7
|
||||
; CHECK-LE-NEXT: .LBB11_8:
|
||||
; CHECK-LE-NEXT: addi r3, r1, -32768
|
||||
; CHECK-LE-NEXT: lbz r3, 0(r3)
|
||||
; CHECK-LE-NEXT: ld r1, 0(r1)
|
||||
; CHECK-LE-NEXT: ld r31, -8(r1)
|
||||
; CHECK-LE-NEXT: ld r30, -16(r1)
|
||||
; CHECK-LE-NEXT: blr
|
||||
;
|
||||
; CHECK-BE-LABEL: f11:
|
||||
; CHECK-BE: # %bb.0:
|
||||
; CHECK-BE-NEXT: std r31, -8(r1)
|
||||
; CHECK-BE-NEXT: std r30, -16(r1)
|
||||
; CHECK-BE-NEXT: mr r30, r1
|
||||
; CHECK-BE-NEXT: .cfi_def_cfa r30, 0
|
||||
; CHECK-BE-NEXT: clrldi r0, r30, 49
|
||||
; CHECK-BE-NEXT: subc r12, r30, r0
|
||||
; CHECK-BE-NEXT: clrldi r0, r0, 52
|
||||
; CHECK-BE-NEXT: cmpdi r0, 0
|
||||
; CHECK-BE-NEXT: beq cr0, .LBB11_2
|
||||
; CHECK-BE-NEXT: # %bb.1:
|
||||
; CHECK-BE-NEXT: neg r0, r0
|
||||
; CHECK-BE-NEXT: stdux r30, r1, r0
|
||||
; CHECK-BE-NEXT: .LBB11_2:
|
||||
; CHECK-BE-NEXT: li r0, -4096
|
||||
; CHECK-BE-NEXT: cmpd r1, r12
|
||||
; CHECK-BE-NEXT: beq cr0, .LBB11_4
|
||||
; CHECK-BE-NEXT: .LBB11_3:
|
||||
; CHECK-BE-NEXT: stdux r30, r1, r0
|
||||
; CHECK-BE-NEXT: cmpd r1, r12
|
||||
; CHECK-BE-NEXT: bne cr0, .LBB11_3
|
||||
; CHECK-BE-NEXT: .LBB11_4:
|
||||
; CHECK-BE-NEXT: mr r12, r30
|
||||
; CHECK-BE-NEXT: li r0, 24
|
||||
; CHECK-BE-NEXT: mtctr r0
|
||||
; CHECK-BE-NEXT: .LBB11_5:
|
||||
; CHECK-BE-NEXT: stdu r12, -4096(r1)
|
||||
; CHECK-BE-NEXT: bdnz .LBB11_5
|
||||
; CHECK-BE-NEXT: # %bb.6:
|
||||
; CHECK-BE-NEXT: .cfi_def_cfa_register r1
|
||||
; CHECK-BE-NEXT: .cfi_def_cfa_register r30
|
||||
; CHECK-BE-NEXT: .cfi_offset r31, -8
|
||||
; CHECK-BE-NEXT: .cfi_offset r30, -16
|
||||
; CHECK-BE-NEXT: clrldi r3, r3, 32
|
||||
; CHECK-BE-NEXT: lis r5, 1
|
||||
; CHECK-BE-NEXT: addi r3, r3, 15
|
||||
; CHECK-BE-NEXT: mr r31, r1
|
||||
; CHECK-BE-NEXT: ori r5, r5, 0
|
||||
; CHECK-BE-NEXT: rldicl r3, r3, 60, 4
|
||||
; CHECK-BE-NEXT: add r5, r31, r5
|
||||
; CHECK-BE-NEXT: sldi r4, r4, 2
|
||||
; CHECK-BE-NEXT: li r6, 1
|
||||
; CHECK-BE-NEXT: rldicl r3, r3, 4, 31
|
||||
; CHECK-BE-NEXT: stwx r6, r5, r4
|
||||
; CHECK-BE-NEXT: neg r7, r3
|
||||
; CHECK-BE-NEXT: li r4, -32768
|
||||
; CHECK-BE-NEXT: and r4, r7, r4
|
||||
; CHECK-BE-NEXT: ld r3, 0(r1)
|
||||
; CHECK-BE-NEXT: mr r7, r4
|
||||
; CHECK-BE-NEXT: li r4, -4096
|
||||
; CHECK-BE-NEXT: divd r5, r7, r4
|
||||
; CHECK-BE-NEXT: mulld r4, r5, r4
|
||||
; CHECK-BE-NEXT: sub r5, r7, r4
|
||||
; CHECK-BE-NEXT: add r4, r1, r7
|
||||
; CHECK-BE-NEXT: stdux r3, r1, r5
|
||||
; CHECK-BE-NEXT: cmpd r1, r4
|
||||
; CHECK-BE-NEXT: beq cr0, .LBB11_8
|
||||
; CHECK-BE-NEXT: .LBB11_7:
|
||||
; CHECK-BE-NEXT: stdu r3, -4096(r1)
|
||||
; CHECK-BE-NEXT: cmpd r1, r4
|
||||
; CHECK-BE-NEXT: bne cr0, .LBB11_7
|
||||
; CHECK-BE-NEXT: .LBB11_8:
|
||||
; CHECK-BE-NEXT: addi r3, r1, -32768
|
||||
; CHECK-BE-NEXT: lbz r3, 0(r3)
|
||||
; CHECK-BE-NEXT: ld r1, 0(r1)
|
||||
; CHECK-BE-NEXT: ld r31, -8(r1)
|
||||
; CHECK-BE-NEXT: ld r30, -16(r1)
|
||||
; CHECK-BE-NEXT: blr
|
||||
;
|
||||
; CHECK-32-LABEL: f11:
|
||||
; CHECK-32: # %bb.0:
|
||||
; CHECK-32-NEXT: mr r12, r1
|
||||
; CHECK-32-NEXT: .cfi_def_cfa r12, 0
|
||||
; CHECK-32-NEXT: clrlwi r0, r12, 17
|
||||
; CHECK-32-NEXT: subc r1, r1, r0
|
||||
; CHECK-32-NEXT: li r0, 24
|
||||
; CHECK-32-NEXT: mtctr r0
|
||||
; CHECK-32-NEXT: .LBB11_1:
|
||||
; CHECK-32-NEXT: stwu r12, -4096(r1)
|
||||
; CHECK-32-NEXT: bdnz .LBB11_1
|
||||
; CHECK-32-NEXT: # %bb.2:
|
||||
; CHECK-32-NEXT: .cfi_def_cfa_register r1
|
||||
; CHECK-32-NEXT: sub r0, r1, r12
|
||||
; CHECK-32-NEXT: sub r0, r1, r0
|
||||
; CHECK-32-NEXT: addic r0, r0, -4
|
||||
; CHECK-32-NEXT: stwx r31, 0, r0
|
||||
; CHECK-32-NEXT: addic r0, r0, -4
|
||||
; CHECK-32-NEXT: stwx r30, 0, r0
|
||||
; CHECK-32-NEXT: addic r30, r0, 8
|
||||
; CHECK-32-NEXT: .cfi_def_cfa_register r30
|
||||
; CHECK-32-NEXT: .cfi_offset r31, -4
|
||||
; CHECK-32-NEXT: .cfi_offset r30, -8
|
||||
; CHECK-32-NEXT: lis r4, 1
|
||||
; CHECK-32-NEXT: mr r31, r1
|
||||
; CHECK-32-NEXT: ori r4, r4, 0
|
||||
; CHECK-32-NEXT: addi r3, r3, 15
|
||||
; CHECK-32-NEXT: add r4, r31, r4
|
||||
; CHECK-32-NEXT: li r5, 1
|
||||
; CHECK-32-NEXT: slwi r6, r6, 2
|
||||
; CHECK-32-NEXT: rlwinm r3, r3, 0, 0, 27
|
||||
; CHECK-32-NEXT: neg r7, r3
|
||||
; CHECK-32-NEXT: stwx r5, r4, r6
|
||||
; CHECK-32-NEXT: li r4, -32768
|
||||
; CHECK-32-NEXT: and r4, r7, r4
|
||||
; CHECK-32-NEXT: lwz r3, 0(r1)
|
||||
; CHECK-32-NEXT: mr r7, r4
|
||||
; CHECK-32-NEXT: li r4, -4096
|
||||
; CHECK-32-NEXT: divw r5, r7, r4
|
||||
; CHECK-32-NEXT: mullw r4, r5, r4
|
||||
; CHECK-32-NEXT: sub r5, r7, r4
|
||||
; CHECK-32-NEXT: add r4, r1, r7
|
||||
; CHECK-32-NEXT: stwux r3, r1, r5
|
||||
; CHECK-32-NEXT: cmpw r1, r4
|
||||
; CHECK-32-NEXT: beq cr0, .LBB11_4
|
||||
; CHECK-32-NEXT: .LBB11_3:
|
||||
; CHECK-32-NEXT: stwu r3, -4096(r1)
|
||||
; CHECK-32-NEXT: cmpw r1, r4
|
||||
; CHECK-32-NEXT: bne cr0, .LBB11_3
|
||||
; CHECK-32-NEXT: .LBB11_4:
|
||||
; CHECK-32-NEXT: addi r3, r1, -32768
|
||||
; CHECK-32-NEXT: lbz r3, 0(r3)
|
||||
; CHECK-32-NEXT: lwz r31, 0(r1)
|
||||
; CHECK-32-NEXT: lwz r0, -4(r31)
|
||||
; CHECK-32-NEXT: lwz r30, -8(r31)
|
||||
; CHECK-32-NEXT: mr r1, r31
|
||||
; CHECK-32-NEXT: mr r31, r0
|
||||
; CHECK-32-NEXT: blr
|
||||
%a = alloca i32, i32 4096, align 32768
|
||||
%b = getelementptr inbounds i32, i32* %a, i64 %i
|
||||
store volatile i32 1, i32* %b
|
||||
%1 = zext i32 %vla_size to i64
|
||||
%vla = alloca i8, i64 %1, align 2048
|
||||
%2 = load volatile i8, i8* %vla, align 2048
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { "probe-stack"="inline-asm" }
|
||||
|
|
|
|||
Loading…
Reference in New Issue