forked from OSchip/llvm-project
[AVR] Redefine the 'SBR' instruction as an alias
This fixes a TableGen warning about duplicate bit patterns. SBR === This is an alias of 'ORI Rd, K'. llvm-svn: 341277
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@ -732,6 +732,14 @@ Defs = [SREG] in
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// This operation is identical to a `Rd AND Rd`.
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def : InstAlias<"tst\t$rd", (ANDRdRr GPR8:$rd, GPR8:$rd)>;
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// SBR Rd, K
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//
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// Mnemonic alias to 'ORI Rd, K'. Same bit pattern, same operands,
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// same everything.
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def : InstAlias<"sbr\t$rd, $k",
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(ORIRdK LD8:$rd, imm_ldi8:$k),
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/* Disable display, so we don't override ORI */ 0>;
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//===----------------------------------------------------------------------===//
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// Jump instructions
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//===----------------------------------------------------------------------===//
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@ -1730,15 +1738,6 @@ def BLD : FRdB<0b00,
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let Constraints = "$src = $rd",
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Defs = [SREG] in
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{
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// SBR Rd, K
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// Alias for ORI Rd, K
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def SBRRdK : FRdK<0b0110,
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(outs LD8:$rd),
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(ins LD8:$src, imm_ldi8:$k),
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"sbr\t$rd, $k",
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[(set i8:$rd, (or i8:$src, imm:$k)),
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(implicit SREG)]>;
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// CBR Rd, K
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// Alias for `ANDI Rd, COM(K)` where COM(K) is the complement of K.
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// FIXME: This uses the 'complement' encoder. We need it to also use the
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@ -9,10 +9,10 @@ foo:
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sbr r19, _start
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; CHECK: sbr r17, 208 ; encoding: [0x10,0x6d]
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; CHECK: sbr r24, 190 ; encoding: [0x8e,0x6b]
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; CHECK: sbr r20, 173 ; encoding: [0x4d,0x6a]
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; CHECK: sbr r31, 0 ; encoding: [0xf0,0x60]
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; CHECK: ori r17, 208 ; encoding: [0x10,0x6d]
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; CHECK: ori r24, 190 ; encoding: [0x8e,0x6b]
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; CHECK: ori r20, 173 ; encoding: [0x4d,0x6a]
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; CHECK: ori r31, 0 ; encoding: [0xf0,0x60]
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; CHECK: sbr r19, _start ; encoding: [0x30'A',0x60]
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; CHECK: ori r19, _start ; encoding: [0x30'A',0x60]
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; CHECK: ; fixup A - offset: 0, value: _start, kind: fixup_ldi
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