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Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits. 

LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned.  Radar 8489376.

llvm-svn: 115047
This commit is contained in:
Bob Wilson 2010-09-29 17:54:10 +00:00
parent 620f9d1548
commit 97bf273870
3 changed files with 5 additions and 5 deletions
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2
llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@ -1370,7 +1370,7 @@ ARMPreAllocLoadStoreOpt::CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1,
unsigned Align = (*Op0->memoperands_begin())->getAlignment();
const Function *Func = MF->getFunction();
unsigned ReqAlign = STI->hasV6Ops()
? TD->getPrefTypeAlignment(Type::getInt64Ty(Func->getContext()))
? TD->getABITypeAlignment(Type::getInt64Ty(Func->getContext()))
: 8; // Pre-v6 need 8-byte align
if (Align < ReqAlign)
return false;

4
llvm/lib/Target/ARM/ARMSubtarget.h
View File

@ -218,7 +218,7 @@ protected:
std::string getDataLayout() const {
if (isThumb()) {
if (isAPCS_ABI()) {
return std::string("e-p:32:32-f64:32:32-i64:32:32-"
return std::string("e-p:32:32-f64:32:64-i64:32:64-"
"i16:16:32-i8:8:32-i1:8:32-"
"v128:32:128-v64:32:64-a:0:32-n32");
} else {
@ -228,7 +228,7 @@ protected:
}
} else {
if (isAPCS_ABI()) {
return std::string("e-p:32:32-f64:32:32-i64:32:32-"
return std::string("e-p:32:32-f64:32:64-i64:32:64-"
"v128:32:128-v64:32:64-n32");
} else {
return std::string("e-p:32:32-f64:64:64-i64:64:64-"

4
llvm/test/CodeGen/ARM/align.ll
View File

@ -22,7 +22,7 @@
@e = global i64 4
;ELF: .align 3
;ELF: e
;DARWIN: .align 2
;DARWIN: .align 3
;DARWIN: _e:
@f = global float 5.0
@ -34,7 +34,7 @@
@g = global double 6.0
;ELF: .align 3
;ELF: g:
;DARWIN: .align 2
;DARWIN: .align 3
;DARWIN: _g:
@bar = common global [75 x i8] zeroinitializer, align 128