forked from OSchip/llvm-project
[Modules] Fix potential ODR violations by sinking the DEBUG_TYPE
definition below all of the header #include lines, TableGen edition. llvm-svn: 206846
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@ -13,8 +13,6 @@
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "ctags-emitter"
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#include "llvm/Support/SourceMgr.h"
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#include "llvm/Support/MemoryBuffer.h"
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#include "llvm/TableGen/Error.h"
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@ -24,6 +22,8 @@
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#include <vector>
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using namespace llvm;
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#define DEBUG_TYPE "ctags-emitter"
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namespace llvm { extern SourceMgr SrcMgr; }
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namespace {
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@ -12,8 +12,6 @@
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc-emitter"
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#include "CodeGenRegisters.h"
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#include "CodeGenTarget.h"
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#include "llvm/ADT/IntEqClasses.h"
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@ -26,6 +24,8 @@
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using namespace llvm;
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#define DEBUG_TYPE "regalloc-emitter"
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//===----------------------------------------------------------------------===//
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// CodeGenSubRegIndex
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//===----------------------------------------------------------------------===//
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@ -12,8 +12,6 @@
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "subtarget-emitter"
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#include "CodeGenSchedule.h"
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#include "CodeGenTarget.h"
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#include "llvm/ADT/STLExtras.h"
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@ -23,6 +21,8 @@
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using namespace llvm;
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#define DEBUG_TYPE "subtarget-emitter"
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#ifndef NDEBUG
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static void dumpIdxVec(const IdxVec &V) {
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for (unsigned i = 0, e = V.size(); i < e; ++i) {
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@ -11,7 +11,6 @@
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "isel-opt"
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#include "DAGISelMatcher.h"
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#include "CodeGenDAGPatterns.h"
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#include "llvm/ADT/DenseSet.h"
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@ -20,6 +19,8 @@
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "isel-opt"
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/// ContractNodes - Turn multiple matcher node patterns like 'MoveChild+Record'
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/// into single compound nodes like RecordChild.
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static void ContractNodes(std::unique_ptr<Matcher> &MatcherPtr,
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@ -12,8 +12,6 @@
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "decoder-emitter"
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#include "CodeGenTarget.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/SmallString.h"
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@ -34,6 +32,8 @@
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using namespace llvm;
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#define DEBUG_TYPE "decoder-emitter"
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namespace {
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struct EncodingField {
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unsigned Base, Width, Offset;
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@ -7,7 +7,6 @@
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "pseudo-lowering"
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#include "CodeGenInstruction.h"
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#include "CodeGenTarget.h"
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#include "llvm/ADT/IndexedMap.h"
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@ -21,6 +20,8 @@
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#include <vector>
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using namespace llvm;
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#define DEBUG_TYPE "pseudo-lowering"
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namespace {
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class PseudoLoweringEmitter {
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struct OpData {
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@ -11,8 +11,6 @@
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "subtarget-emitter"
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#include "CodeGenTarget.h"
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#include "CodeGenSchedule.h"
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#include "llvm/ADT/STLExtras.h"
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@ -29,6 +27,8 @@
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#include <vector>
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using namespace llvm;
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#define DEBUG_TYPE "subtarget-emitter"
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namespace {
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class SubtargetEmitter {
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// Each processor has a SchedClassDesc table with an entry for each SchedClass.
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