forked from OSchip/llvm-project
[X86] Add a FIXME about why the CWD/CDQ/CQO have a bogus implicit def of the A register. NFC
The instructions copy the sign bit of the A register to every bit of the D register. But they don't write to the A register. llvm-svn: 371094
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@ -17,19 +17,18 @@ let hasSideEffects = 0 in {
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let Defs = [EAX], Uses = [AX] in // EAX = signext(AX)
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let Defs = [EAX], Uses = [AX] in // EAX = signext(AX)
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def CWDE : I<0x98, RawFrm, (outs), (ins),
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def CWDE : I<0x98, RawFrm, (outs), (ins),
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"{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
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"{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
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let Defs = [RAX], Uses = [EAX] in // RAX = signext(EAX)
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def CDQE : RI<0x98, RawFrm, (outs), (ins),
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"{cltq|cdqe}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>;
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// FIXME: CWD/CDQ/CQO shouldn't Def the A register, but the fast register
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// allocator crashes if you remove it.
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let Defs = [AX,DX], Uses = [AX] in // DX:AX = signext(AX)
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let Defs = [AX,DX], Uses = [AX] in // DX:AX = signext(AX)
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def CWD : I<0x99, RawFrm, (outs), (ins),
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def CWD : I<0x99, RawFrm, (outs), (ins),
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"{cwtd|cwd}", []>, OpSize16, Sched<[WriteALU]>;
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"{cwtd|cwd}", []>, OpSize16, Sched<[WriteALU]>;
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let Defs = [EAX,EDX], Uses = [EAX] in // EDX:EAX = signext(EAX)
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let Defs = [EAX,EDX], Uses = [EAX] in // EDX:EAX = signext(EAX)
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def CDQ : I<0x99, RawFrm, (outs), (ins),
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def CDQ : I<0x99, RawFrm, (outs), (ins),
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"{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
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"{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
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let Defs = [RAX], Uses = [EAX] in // RAX = signext(EAX)
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def CDQE : RI<0x98, RawFrm, (outs), (ins),
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"{cltq|cdqe}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>;
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let Defs = [RAX,RDX], Uses = [RAX] in // RDX:RAX = signext(RAX)
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let Defs = [RAX,RDX], Uses = [RAX] in // RDX:RAX = signext(RAX)
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def CQO : RI<0x99, RawFrm, (outs), (ins),
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def CQO : RI<0x99, RawFrm, (outs), (ins),
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"{cqto|cqo}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>;
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"{cqto|cqo}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>;
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