forked from OSchip/llvm-project
X86InstrInfo: Optimize more combinations of SUB+CMP
`X86InstrInfo::optimizeCompareInstr` would only optimize a `SUB` followed by a `CMP` in `isRedundantFlagInstr`. This extends the code to also look for other combinations like `CMP`+`CMP`, `TEST`+`TEST`, `SUB x,0`+`TEST`. - Change `isRedundantFlagInstr` to run `analyzeCompareInstr` on the candidate instruction and compare the results. This normalizes things and gives consistent results for various comparisons (`CMP x, y`, `SUB x, y`) and immediate cases (`TEST x, x`, `SUB x, 0`, `CMP x, 0`...). - Turn `isRedundantFlagInstr` into a member function so it can call `analyzeCompare`. - We now also check `isRedundantFlagInstr` even if `IsCmpZero` is true, since we now have cases like `TEST`+`TEST`. Differential Revision: https://reviews.llvm.org/D110865
This commit is contained in:
Matthias Braun
parent
e50f02ba7e
commit
97a1570d8c
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@ -4011,42 +4011,72 @@ bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
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return false;
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}
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/// Check whether the first instruction, whose only
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/// purpose is to update flags, can be made redundant.
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/// CMPrr can be made redundant by SUBrr if the operands are the same.
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/// This function can be extended later on.
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/// SrcReg, SrcRegs: register operands for FlagI.
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/// ImmValue: immediate for FlagI if it takes an immediate.
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inline static bool isRedundantFlagInstr(const MachineInstr &FlagI,
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bool X86InstrInfo::isRedundantFlagInstr(const MachineInstr &FlagI,
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Register SrcReg, Register SrcReg2,
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int64_t ImmMask, int64_t ImmValue,
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const MachineInstr &OI) {
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if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
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(FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
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(FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
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(FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
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((OI.getOperand(1).getReg() == SrcReg &&
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OI.getOperand(2).getReg() == SrcReg2) ||
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(OI.getOperand(1).getReg() == SrcReg2 &&
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OI.getOperand(2).getReg() == SrcReg)))
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return true;
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if (ImmMask != 0 &&
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((FlagI.getOpcode() == X86::CMP64ri32 &&
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OI.getOpcode() == X86::SUB64ri32) ||
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(FlagI.getOpcode() == X86::CMP64ri8 &&
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OI.getOpcode() == X86::SUB64ri8) ||
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(FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
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(FlagI.getOpcode() == X86::CMP32ri8 &&
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OI.getOpcode() == X86::SUB32ri8) ||
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(FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
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(FlagI.getOpcode() == X86::CMP16ri8 &&
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OI.getOpcode() == X86::SUB16ri8) ||
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(FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
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OI.getOperand(1).getReg() == SrcReg &&
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OI.getOperand(2).getImm() == ImmValue)
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return true;
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const MachineInstr &OI,
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bool *IsSwapped) const {
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switch (OI.getOpcode()) {
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case X86::CMP64rr:
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case X86::CMP32rr:
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case X86::CMP16rr:
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case X86::CMP8rr:
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case X86::SUB64rr:
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case X86::SUB32rr:
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case X86::SUB16rr:
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case X86::SUB8rr: {
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Register OISrcReg;
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Register OISrcReg2;
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int64_t OIMask;
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int64_t OIValue;
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if (!analyzeCompare(OI, OISrcReg, OISrcReg2, OIMask, OIValue) ||
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OIMask != ImmMask || OIValue != ImmValue)
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return false;
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if (SrcReg == OISrcReg && SrcReg2 == OISrcReg2) {
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*IsSwapped = false;
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return true;
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}
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if (SrcReg == OISrcReg2 && SrcReg2 == OISrcReg) {
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*IsSwapped = true;
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return true;
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}
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return false;
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}
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case X86::CMP64ri32:
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case X86::CMP64ri8:
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case X86::CMP32ri:
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case X86::CMP32ri8:
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case X86::CMP16ri:
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case X86::CMP16ri8:
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case X86::CMP8ri:
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case X86::SUB64ri32:
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case X86::SUB64ri8:
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case X86::SUB32ri:
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case X86::SUB32ri8:
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case X86::SUB16ri:
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case X86::SUB16ri8:
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case X86::SUB8ri:
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case X86::TEST64rr:
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case X86::TEST32rr:
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case X86::TEST16rr:
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case X86::TEST8rr: {
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if (ImmMask != 0) {
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Register OISrcReg;
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Register OISrcReg2;
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int64_t OIMask;
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int64_t OIValue;
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if (analyzeCompare(OI, OISrcReg, OISrcReg2, OIMask, OIValue) &&
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SrcReg == OISrcReg && ImmMask == OIMask && OIValue == ImmValue) {
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assert(SrcReg2 == X86::NoRegister && OISrcReg2 == X86::NoRegister &&
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"should not have 2nd register");
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return true;
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}
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}
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return FlagI.isIdenticalTo(OI);
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}
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default:
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return false;
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}
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}
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/// Check whether the definition can be converted
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@ -4275,12 +4305,19 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
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bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
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// Transformation currently requires SSA values.
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if (SrcReg2.isPhysical())
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return false;
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MachineInstr *SrcRegDef = MRI->getVRegDef(SrcReg);
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assert(SrcRegDef && "Must have a definition (SSA)");
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MachineInstr *MI = nullptr;
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MachineInstr *Sub = nullptr;
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MachineInstr *Movr0Inst = nullptr;
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bool NoSignFlag = false;
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bool ClearsOverflowFlag = false;
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bool ShouldUpdateCC = false;
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bool IsSwapped = false;
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X86::CondCode NewCC = X86::COND_INVALID;
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// Search backward from CmpInstr for the next instruction defining EFLAGS.
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@ -4288,8 +4325,6 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
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MachineBasicBlock &CmpMBB = *CmpInstr.getParent();
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MachineBasicBlock::reverse_iterator From =
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std::next(MachineBasicBlock::reverse_iterator(CmpInstr));
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MachineInstr *SrcRegDef = MRI->getVRegDef(SrcReg);
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assert(SrcRegDef && "Must have a definition (SSA)");
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for (MachineBasicBlock *MBB = &CmpMBB;;) {
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for (MachineInstr &Inst : make_range(From, MBB->rend())) {
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// Try to use EFLAGS from the instruction defining %SrcReg. Example:
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@ -4329,8 +4364,8 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
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// sub x, y or cmp x, y
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// ... // EFLAGS not changed
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// cmp x, y // <-- can be removed
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if (!IsCmpZero && isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2,
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CmpMask, CmpValue, Inst)) {
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if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask, CmpValue,
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Inst, &IsSwapped)) {
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Sub = &Inst;
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break;
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}
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@ -4360,10 +4395,6 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
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From = MBB->rbegin();
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}
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bool IsSwapped =
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(SrcReg2 != 0 && Sub && Sub->getOperand(1).getReg() == SrcReg2 &&
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Sub->getOperand(2).getReg() == SrcReg);
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// Scan forward from the instruction after CmpInstr for uses of EFLAGS.
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// It is safe to remove CmpInstr if EFLAGS is redefined or killed.
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// If we are done with the basic block, we need to check whether EFLAGS is
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@ -4386,7 +4417,7 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
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// EFLAGS is used by this instruction.
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X86::CondCode OldCC = X86::COND_INVALID;
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if (IsCmpZero || IsSwapped) {
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if (MI || IsSwapped) {
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// We decode the condition code from opcode.
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if (Instr.isBranch())
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OldCC = X86::getCondFromBranch(Instr);
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@ -4398,7 +4429,7 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
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if (OldCC == X86::COND_INVALID) return false;
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}
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X86::CondCode ReplacementCC = X86::COND_INVALID;
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if (IsCmpZero) {
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if (MI) {
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switch (OldCC) {
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default: break;
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case X86::COND_A: case X86::COND_AE:
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@ -4456,14 +4487,15 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
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// If EFLAGS is not killed nor re-defined, we should check whether it is
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// live-out. If it is live-out, do not optimize.
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if ((IsCmpZero || IsSwapped) && !IsSafe) {
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if ((MI || IsSwapped) && !IsSafe) {
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for (MachineBasicBlock *Successor : CmpMBB.successors())
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if (Successor->isLiveIn(X86::EFLAGS))
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return false;
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}
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// The instruction to be updated is either Sub or MI.
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Sub = IsCmpZero ? MI : Sub;
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assert((MI == nullptr || Sub == nullptr) && "Should not have Sub and MI set");
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Sub = MI != nullptr ? MI : Sub;
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MachineBasicBlock *SubBB = Sub->getParent();
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// Move Movr0Inst to the appropriate place before Sub.
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if (Movr0Inst) {
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@ -626,6 +626,21 @@ private:
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unsigned &SrcOpIdx1,
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unsigned &SrcOpIdx2,
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bool IsIntrinsic = false) const;
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/// Returns true when instruction \p FlagI produces the same flags as \p OI.
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/// The caller should pass in the results of calling analyzeCompare on \p OI:
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/// \p SrcReg, \p SrcReg2, \p ImmMask, \p ImmValue.
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/// If the flags match \p OI as if it had the input operands swapped then the
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/// function succeeds and sets \p IsSwapped to true.
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///
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/// Examples of OI, FlagI pairs returning true:
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/// CMP %1, 42 and CMP %1, 42
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/// CMP %1, %2 and %3 = SUB %1, %2
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/// TEST %1, %1 and %2 = SUB %1, 0
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/// CMP %1, %2 and %3 = SUB %2, %1 ; IsSwapped=true
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bool isRedundantFlagInstr(const MachineInstr &FlagI, Register SrcReg,
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Register SrcReg2, int64_t ImmMask, int64_t ImmValue,
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const MachineInstr &OI, bool *IsSwapped) const;
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};
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} // namespace llvm
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@ -67,7 +67,6 @@ define i16 @main_bb_2E_i9_2E_i_2E_i932_2E_ce(%struct.list* %l_addr.01.0.i2.i.i92
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; CHECK-NEXT: LBB0_6: ## %NodeBlock
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; CHECK-NEXT: js LBB0_9
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; CHECK-NEXT: ## %bb.7: ## %LeafBlock1
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; CHECK-NEXT: testl %eax, %eax
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; CHECK-NEXT: jne LBB0_3
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; CHECK-NEXT: ## %bb.8: ## %bb12.i.i935.exitStub
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; CHECK-NEXT: movl %edi, (%esi)
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@ -212,8 +212,7 @@ body: |
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $edi
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; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
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; CHECK-NEXT: $cl = SETCCr 2, implicit $eflags
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; CHECK-NEXT: CMP32rr [[COPY1]], [[COPY]], implicit-def $eflags
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; CHECK-NEXT: $bl = SETCCr 2, implicit $eflags
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; CHECK-NEXT: $bl = SETCCr 7, implicit $eflags
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%0:gr32 = COPY $esi
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%1:gr32 = COPY $edi
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CMP32rr %0, %1, implicit-def $eflags
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@ -231,7 +230,6 @@ body: |
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
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; CHECK-NEXT: CMP64ri8 [[COPY]], 15, implicit-def $eflags
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; CHECK-NEXT: $cl = SETCCr 2, implicit $eflags
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; CHECK-NEXT: CMP64ri8 [[COPY]], 15, implicit-def $eflags
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; CHECK-NEXT: $bl = SETCCr 2, implicit $eflags
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%0:gr64 = COPY $rsi
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%1:gr64 = COPY $rdi
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@ -249,7 +247,6 @@ body: |
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; CHECK: [[COPY:%[0-9]+]]:gr16 = COPY $ax
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; CHECK-NEXT: TEST16rr [[COPY]], [[COPY]], implicit-def $eflags
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; CHECK-NEXT: $cl = SETCCr 2, implicit $eflags
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; CHECK-NEXT: TEST16rr [[COPY]], [[COPY]], implicit-def $eflags
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; CHECK-NEXT: $bl = SETCCr 2, implicit $eflags
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%0:gr16 = COPY $ax
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TEST16rr %0, %0, implicit-def $eflags
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@ -267,8 +264,7 @@ body: |
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $edi
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; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
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; CHECK-NEXT: $cl = SETCCr 2, implicit $eflags
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; CHECK-NEXT: CMP32rr [[COPY1]], [[COPY]], implicit-def $eflags
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; CHECK-NEXT: $bl = SETCCr 2, implicit $eflags
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; CHECK-NEXT: $bl = SETCCr 7, implicit $eflags
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%0:gr32 = COPY $esi
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%1:gr32 = COPY $edi
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CMP32rr %0, %1, implicit-def $eflags
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@ -285,7 +281,6 @@ body: |
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $esi
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; CHECK-NEXT: CMP32ri [[COPY]], -12345, implicit-def $eflags
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; CHECK-NEXT: $cl = SETCCr 2, implicit $eflags
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; CHECK-NEXT: CMP32ri [[COPY]], -12345, implicit-def $eflags
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; CHECK-NEXT: $bl = SETCCr 2, implicit $eflags
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%0:gr32 = COPY $esi
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CMP32ri %0, -12345, implicit-def $eflags
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@ -323,7 +318,6 @@ body: |
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $esi
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; CHECK-NEXT: CMP32ri8 [[COPY]], 0, implicit-def $eflags
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; CHECK-NEXT: $cl = SETCCr 2, implicit $eflags
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; CHECK-NEXT: TEST32rr [[COPY]], [[COPY]], implicit-def $eflags
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; CHECK-NEXT: $bl = SETCCr 2, implicit $eflags
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%0:gr32 = COPY $esi
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CMP32ri8 %0, 0, implicit-def $eflags
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $esi
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; CHECK-NEXT: TEST32rr [[COPY]], [[COPY]], implicit-def $eflags
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; CHECK-NEXT: $cl = SETCCr 2, implicit $eflags
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; CHECK-NEXT: CMP32ri8 [[COPY]], 0, implicit-def $eflags
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; CHECK-NEXT: $bl = SETCCr 2, implicit $eflags
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%0:gr32 = COPY $esi
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TEST32rr %0, %0, implicit-def $eflags
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@ -359,7 +352,6 @@ body: |
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; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rsi
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; CHECK-NEXT: CMP64ri32 [[COPY]], @opt_redundant_flags_cmp_addr + 4, implicit-def $eflags
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; CHECK-NEXT: $cl = SETCCr 7, implicit $eflags
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; CHECK-NEXT: CMP64ri32 [[COPY]], @opt_redundant_flags_cmp_addr + 4, implicit-def $eflags
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; CHECK-NEXT: $cl = SETCCr 3, implicit $eflags
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%0:gr64 = COPY $rsi
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CMP64ri32 %0, @opt_redundant_flags_cmp_addr + 4, implicit-def $eflags
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@ -15,7 +15,6 @@ define fastcc i32 @_Z18yy_get_next_bufferv() nounwind {
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; CHECK-NEXT: jne .LBB0_1
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; CHECK-NEXT: .LBB0_3: # %bb158
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; CHECK-NEXT: movb %al, 0
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; CHECK-NEXT: cmpl $-1, %eax
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retl
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entry:
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