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Bug fix. Not advancing the register scavenger iterator correctly. 

llvm-svn: 35020
This commit is contained in:
Evan Cheng 2007-03-08 02:55:08 +00:00
parent bb5741fb02
commit 977195e912
1 changed files with 21 additions and 8 deletions
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29
llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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@ -42,7 +42,6 @@ namespace {
const MRegisterInfo *MRI; const MRegisterInfo *MRI;
ARMFunctionInfo *AFI; ARMFunctionInfo *AFI;
RegScavenger *RS; RegScavenger *RS;
MachineBasicBlock::iterator RSI;
virtual bool runOnMachineFunction(MachineFunction &Fn); virtual bool runOnMachineFunction(MachineFunction &Fn);
@ -67,6 +66,7 @@ namespace {
int Opcode, unsigned Size, unsigned Scratch, int Opcode, unsigned Size, unsigned Scratch,
MemOpQueue &MemOps); MemOpQueue &MemOps);
void AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps);
bool LoadStoreMultipleOpti(MachineBasicBlock &MBB); bool LoadStoreMultipleOpti(MachineBasicBlock &MBB);
bool MergeReturnIntoLDM(MachineBasicBlock &MBB); bool MergeReturnIntoLDM(MachineBasicBlock &MBB);
}; };
@ -492,6 +492,22 @@ static bool isMemoryOp(MachineInstr *MI) {
return false; return false;
} }
/// AdvanceRS - Advance register scavenger to just before the earliest memory
/// op that is being merged.
void ARMLoadStoreOpt::AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps) {
MachineBasicBlock::iterator Loc = MemOps[0].MBBI;
unsigned Position = MemOps[0].Position;
for (unsigned i = 1, e = MemOps.size(); i != e; ++i) {
if (MemOps[i].Position < Position) {
Position = MemOps[i].Position;
Loc = MemOps[i].MBBI;
}
}
if (Loc != MBB.begin())
RS->forward(prior(Loc));
}
/// LoadStoreMultipleOpti - An optimization pass to turn multiple LDR / STR /// LoadStoreMultipleOpti - An optimization pass to turn multiple LDR / STR
/// ops of the same base and incrementing offset into LDM / STM ops. /// ops of the same base and incrementing offset into LDM / STM ops.
bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) { bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
@ -504,7 +520,6 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
unsigned Position = 0; unsigned Position = 0;
RS->enterBasicBlock(&MBB); RS->enterBasicBlock(&MBB);
RSI = MBB.begin();
MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
while (MBBI != E) { while (MBBI != E) {
bool Advance = false; bool Advance = false;
@ -585,15 +600,14 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
if (TryMerge) { if (TryMerge) {
if (NumMemOps > 1) { if (NumMemOps > 1) {
// Try to find a free register to use as a new base in case it's needed. // Try to find a free register to use as a new base in case it's needed.
unsigned Scratch = ARM::R12;
// First advance to the instruction just before the start of the chain. // First advance to the instruction just before the start of the chain.
if (RSI != MBB.begin()) AdvanceRS(MBB, MemOps);
RS->forward(prior(RSI));
// Find a scratch register. Make sure it's a call clobbered register or // Find a scratch register. Make sure it's a call clobbered register or
// a spilled callee-saved register. // a spilled callee-saved register.
Scratch = RS->FindUnusedReg(&ARM::GPRRegClass, true); unsigned Scratch = RS->FindUnusedReg(&ARM::GPRRegClass, true);
if (!Scratch) if (!Scratch)
RS->FindUnusedReg(&ARM::GPRRegClass, AFI->getSpilledCSRegisters()); Scratch = RS->FindUnusedReg(&ARM::GPRRegClass,
AFI->getSpilledCSRegisters());
// Process the load / store instructions. // Process the load / store instructions.
RS->forward(prior(MBBI)); RS->forward(prior(MBBI));
@ -617,7 +631,6 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
// RS may be pointing to an instruction that's deleted. // RS may be pointing to an instruction that's deleted.
RS->skipTo(prior(MBBI)); RS->skipTo(prior(MBBI));
RSI = MBBI;
} }
CurrBase = 0; CurrBase = 0;