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[AArch64][GlobalISel] Mark G_INTRINSIC_ROUND as a pre-isel floating point opcode 

Add G_INTRINSIC_ROUND to isPreISelGenericFloatingPointOpcode to ensure that its
input and output are assigned the correct register bank.

Add a regbankselect test to verify that we get what we expect here.

llvm-svn: 359044
This commit is contained in:
Jessica Paquette 2019-04-23 22:47:00 +00:00
parent 312b5f86b7
commit 9766bf1854
2 changed files with 197 additions and 0 deletions
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1
llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
View File

@ -407,6 +407,7 @@ static bool isPreISelGenericFloatingPointOpcode(unsigned Opc) {
case TargetOpcode::G_FEXP:
case TargetOpcode::G_FRINT:
case TargetOpcode::G_INTRINSIC_TRUNC:
case TargetOpcode::G_INTRINSIC_ROUND:
return true;
}
return false;

196
llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-round.mir Normal file
View File

@ -0,0 +1,196 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=regbankselect -mattr=+fullfp16 %s -o - | FileCheck %s
# CHECK-NOT: gpr
...
---
name: test_f16.round
alignment: 2
legalized: true
tracksRegLiveness: true
frameInfo:
maxCallFrameSize: 0
machineFunctionInfo: {}
body: |
bb.0:
liveins: $h0
; CHECK-LABEL: name: test_f16.round
; CHECK: liveins: $h0
; CHECK: [[COPY:%[0-9]+]]:fpr(s16) = COPY $h0
; CHECK: [[INTRINSIC_ROUND:%[0-9]+]]:fpr(s16) = G_INTRINSIC_ROUND [[COPY]]
; CHECK: $h0 = COPY [[INTRINSIC_ROUND]](s16)
; CHECK: RET_ReallyLR implicit $h0
%0:_(s16) = COPY $h0
%1:_(s16) = G_INTRINSIC_ROUND %0
$h0 = COPY %1(s16)
RET_ReallyLR implicit $h0
...
---
name: test_f32.round
alignment: 2
legalized: true
tracksRegLiveness: true
frameInfo:
maxCallFrameSize: 0
machineFunctionInfo: {}
body: |
bb.0:
liveins: $s0
; CHECK-LABEL: name: test_f32.round
; CHECK: liveins: $s0
; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
; CHECK: [[INTRINSIC_ROUND:%[0-9]+]]:fpr(s32) = G_INTRINSIC_ROUND [[COPY]]
; CHECK: $s0 = COPY [[INTRINSIC_ROUND]](s32)
; CHECK: RET_ReallyLR implicit $s0
%0:_(s32) = COPY $s0
%1:_(s32) = G_INTRINSIC_ROUND %0
$s0 = COPY %1(s32)
RET_ReallyLR implicit $s0
...
---
name: test_f64.round
alignment: 2
legalized: true
tracksRegLiveness: true
frameInfo:
maxCallFrameSize: 0
machineFunctionInfo: {}
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: test_f64.round
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0
; CHECK: [[INTRINSIC_ROUND:%[0-9]+]]:fpr(s64) = G_INTRINSIC_ROUND [[COPY]]
; CHECK: $d0 = COPY [[INTRINSIC_ROUND]](s64)
; CHECK: RET_ReallyLR implicit $d0
%0:_(s64) = COPY $d0
%1:_(s64) = G_INTRINSIC_ROUND %0
$d0 = COPY %1(s64)
RET_ReallyLR implicit $d0
...
---
name: test_v8f16.round
alignment: 2
legalized: true
tracksRegLiveness: true
frameInfo:
maxCallFrameSize: 0
machineFunctionInfo: {}
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_v8f16.round
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr(<8 x s16>) = COPY $q0
; CHECK: [[INTRINSIC_ROUND:%[0-9]+]]:fpr(<8 x s16>) = G_INTRINSIC_ROUND [[COPY]]
; CHECK: $q0 = COPY [[INTRINSIC_ROUND]](<8 x s16>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<8 x s16>) = COPY $q0
%1:_(<8 x s16>) = G_INTRINSIC_ROUND %0
$q0 = COPY %1(<8 x s16>)
RET_ReallyLR implicit $q0
...
---
name: test_v4f16.round
alignment: 2
legalized: true
tracksRegLiveness: true
frameInfo:
maxCallFrameSize: 0
machineFunctionInfo: {}
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: test_v4f16.round
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s16>) = COPY $d0
; CHECK: [[INTRINSIC_ROUND:%[0-9]+]]:fpr(<4 x s16>) = G_INTRINSIC_ROUND [[COPY]]
; CHECK: $d0 = COPY [[INTRINSIC_ROUND]](<4 x s16>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = G_INTRINSIC_ROUND %0
$d0 = COPY %1(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: test_v2f32.round
alignment: 2
legalized: true
tracksRegLiveness: true
frameInfo:
maxCallFrameSize: 0
machineFunctionInfo: {}
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: test_v2f32.round
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr(<2 x s32>) = COPY $d0
; CHECK: [[INTRINSIC_ROUND:%[0-9]+]]:fpr(<2 x s32>) = G_INTRINSIC_ROUND [[COPY]]
; CHECK: $d0 = COPY [[INTRINSIC_ROUND]](<2 x s32>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = G_INTRINSIC_ROUND %0
$d0 = COPY %1(<2 x s32>)
RET_ReallyLR implicit $d0
...
---
name: test_v4f32.round
alignment: 2
legalized: true
tracksRegLiveness: true
frameInfo:
maxCallFrameSize: 0
machineFunctionInfo: {}
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_v4f32.round
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
; CHECK: [[INTRINSIC_ROUND:%[0-9]+]]:fpr(<4 x s32>) = G_INTRINSIC_ROUND [[COPY]]
; CHECK: $q0 = COPY [[INTRINSIC_ROUND]](<4 x s32>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<4 x s32>) = COPY $q0
%1:_(<4 x s32>) = G_INTRINSIC_ROUND %0
$q0 = COPY %1(<4 x s32>)
RET_ReallyLR implicit $q0
...
---
name: test_v2f64.round
alignment: 2
legalized: true
tracksRegLiveness: true
frameInfo:
maxCallFrameSize: 0
machineFunctionInfo: {}
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_v2f64.round
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr(<2 x s64>) = COPY $q0
; CHECK: [[INTRINSIC_ROUND:%[0-9]+]]:fpr(<2 x s64>) = G_INTRINSIC_ROUND [[COPY]]
; CHECK: $q0 = COPY [[INTRINSIC_ROUND]](<2 x s64>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<2 x s64>) = COPY $q0
%1:_(<2 x s64>) = G_INTRINSIC_ROUND %0
$q0 = COPY %1(<2 x s64>)
RET_ReallyLR implicit $q0