forked from OSchip/llvm-project
AMDGPU/GlobalISel: Add SReg_96 to SGPRRegBank
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//===----------------------------------------------------------------------===//
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def SGPRRegBank : RegisterBank<"SGPR",
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[SReg_LO16, SReg_32, SReg_64, SReg_128, SReg_160, SReg_192, SReg_256, SReg_512, SReg_1024]
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[SReg_LO16, SReg_32, SReg_64, SReg_96, SReg_128, SReg_160, SReg_192, SReg_256, SReg_512, SReg_1024]
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>;
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def VGPRRegBank : RegisterBank<"VGPR",
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