forked from OSchip/llvm-project
Redo THUMB support.
Discussed with and tested by: Saleem Abdulrasool llvm-svn: 213481
This commit is contained in:
Joerg Sonnenberger
parent
09f45ca39b
commit
9720fcf4bf
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@ -17,6 +17,18 @@
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.syntax unified
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.text
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#if __ARM_ARCH_ISA_THUMB == 2
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.thumb
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#endif
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#if __ARM_ARCH_ISA_THUMB == 2
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#define IT(cond) it cond
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#define ITT(cond) itt cond
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#else
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#define IT(cond)
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#define ITT(cond)
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#endif
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.p2align 2
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DEFINE_COMPILERRT_FUNCTION(__udivmodsi4)
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#if __ARM_ARCH_EXT_IDIV__
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@ -42,6 +54,7 @@ DEFINE_COMPILERRT_FUNCTION(__udivmodsi4)
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* r0 and (r1 << I) have the highest bit set in the same position.
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* At the time of JMP, ip := .Ldiv0block - 12 * I.
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* This depends on the fixed instruction size of block.
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* For ARM mode, this is 12 Bytes, for THUMB mode 14 Bytes.
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*
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* block(shift) implements the test-and-update-quotient core.
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* It assumes (r0 << shift) can be computed without overflow and
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@ -53,12 +66,20 @@ DEFINE_COMPILERRT_FUNCTION(__udivmodsi4)
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clz r3, r1
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/* r0 >= r1 implies clz(r0) <= clz(r1), so ip <= r3. */
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sub r3, r3, ip
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# if __ARM_ARCH_ISA_THUMB == 2
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adr ip, LOCAL_LABEL(div0block) + 1
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sub ip, ip, r3, lsl #1
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# else
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adr ip, LOCAL_LABEL(div0block)
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# endif
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sub ip, ip, r3, lsl #2
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sub ip, ip, r3, lsl #3
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mov r3, #0
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bx ip
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# else
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# if __ARM_ARCH_ISA_THUMB == 2
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# error THUMB mode requires CLZ or UDIV
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# endif
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str r4, [sp, #-8]!
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mov r4, r0
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@ -98,8 +119,9 @@ DEFINE_COMPILERRT_FUNCTION(__udivmodsi4)
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#define block(shift) \
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cmp r0, r1, lsl IMM shift; \
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addhs r3, r3, IMM (1 << shift); \
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subhs r0, r0, r1, lsl IMM shift
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ITT(hs); \
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addhs.w r3, r3, IMM (1 << shift); \
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subhs.w r0, r0, r1, lsl IMM shift
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block(31)
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block(30)
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@ -17,6 +17,18 @@
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.syntax unified
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.text
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#if __ARM_ARCH_ISA_THUMB == 2
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.thumb
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#endif
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#if __ARM_ARCH_ISA_THUMB == 2
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#define IT(cond) it cond
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#define ITT(cond) itt cond
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#else
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#define IT(cond)
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#define ITT(cond)
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#endif
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.p2align 2
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DEFINE_AEABI_FUNCTION_ALIAS(__aeabi_uidiv, __udivsi3)
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DEFINE_COMPILERRT_FUNCTION(__udivsi3)
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@ -30,8 +42,10 @@ DEFINE_COMPILERRT_FUNCTION(__udivsi3)
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#else
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cmp r1, #1
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bcc LOCAL_LABEL(divby0)
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IT(eq)
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JMPc(lr, eq)
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cmp r0, r1
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ITT(cc)
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movcc r0, #0
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JMPc(lr, cc)
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/*
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@ -43,6 +57,7 @@ DEFINE_COMPILERRT_FUNCTION(__udivsi3)
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* r0 and (r1 << I) have the highest bit set in the same position.
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* At the time of JMP, ip := .Ldiv0block - 12 * I.
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* This depends on the fixed instruction size of block.
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* For ARM mode, this is 12 Bytes, for THUMB mode 14 Bytes.
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*
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* block(shift) implements the test-and-update-quotient core.
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* It assumes (r0 << shift) can be computed without overflow and
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@ -54,12 +69,20 @@ DEFINE_COMPILERRT_FUNCTION(__udivsi3)
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clz r3, r1
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/* r0 >= r1 implies clz(r0) <= clz(r1), so ip <= r3. */
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sub r3, r3, ip
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# if __ARM_ARCH_ISA_THUMB == 2
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adr ip, LOCAL_LABEL(div0block) + 1
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sub ip, ip, r3, lsl #1
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# else
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adr ip, LOCAL_LABEL(div0block)
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# endif
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sub ip, ip, r3, lsl #2
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sub ip, ip, r3, lsl #3
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mov r3, #0
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bx ip
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# else
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# if __ARM_ARCH_ISA_THUMB == 2
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# error THUMB mode requires CLZ or UDIV
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# endif
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mov r2, r0
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adr ip, LOCAL_LABEL(div0block)
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@ -96,8 +119,9 @@ DEFINE_COMPILERRT_FUNCTION(__udivsi3)
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#define block(shift) \
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cmp r0, r1, lsl IMM shift; \
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addhs r3, r3, IMM (1 << shift); \
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subhs r0, r0, r1, lsl IMM shift
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ITT(hs); \
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addhs.w r3, r3, IMM (1 << shift); \
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subhs.w r0, r0, r1, lsl IMM shift
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block(31)
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block(30)
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@ -16,6 +16,17 @@
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.syntax unified
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.text
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#if __ARM_ARCH_ISA_THUMB == 2
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.thumb
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#endif
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#if __ARM_ARCH_ISA_THUMB == 2
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#define IT(cond) it cond
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#define ITT(cond) itt cond
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#else
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#define IT(cond)
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#define ITT(cond)
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#endif
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.p2align 2
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DEFINE_COMPILERRT_FUNCTION(__umodsi3)
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@ -30,9 +41,11 @@ DEFINE_COMPILERRT_FUNCTION(__umodsi3)
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#else
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cmp r1, #1
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bcc LOCAL_LABEL(divby0)
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ITT(eq)
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moveq r0, #0
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JMPc(lr, eq)
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cmp r0, r1
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IT(cc)
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JMPc(lr, cc)
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/*
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* Implement division using binary long division algorithm.
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@ -43,6 +56,7 @@ DEFINE_COMPILERRT_FUNCTION(__umodsi3)
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* r0 and (r1 << I) have the highest bit set in the same position.
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* At the time of JMP, ip := .Ldiv0block - 8 * I.
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* This depends on the fixed instruction size of block.
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* For ARM mode, this is 8 Bytes, for THUMB mode 10 Bytes.
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*
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* block(shift) implements the test-and-update-quotient core.
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* It assumes (r0 << shift) can be computed without overflow and
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@ -54,10 +68,18 @@ DEFINE_COMPILERRT_FUNCTION(__umodsi3)
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clz r3, r1
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/* r0 >= r1 implies clz(r0) <= clz(r1), so ip <= r3. */
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sub r3, r3, ip
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# if __ARM_ARCH_ISA_THUMB == 2
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adr ip, LOCAL_LABEL(div0block) + 1
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sub ip, ip, r3, lsl #1
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# else
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adr ip, LOCAL_LABEL(div0block)
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# endif
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sub ip, ip, r3, lsl #3
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bx ip
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# else
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# if __ARM_ARCH_ISA_THUMB == 2
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# error THUMB mode requires CLZ or UDIV
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# endif
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mov r2, r0
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adr ip, LOCAL_LABEL(div0block)
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@ -90,9 +112,10 @@ DEFINE_COMPILERRT_FUNCTION(__umodsi3)
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#define IMM #
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#define block(shift) \
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cmp r0, r1, lsl IMM shift; \
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subhs r0, r0, r1, lsl IMM shift
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#define block(shift) \
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cmp r0, r1, lsl IMM shift; \
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IT(hs); \
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subhs.w r0, r0, r1, lsl IMM shift
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block(31)
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block(30)
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