forked from OSchip/llvm-project
[AMDGPU][GlobalISel] Insert an and with exec before s_cbranch_vccnz if necessary
While v_cmp will AND inactive lanes with 0, that is not the case for logical operations. This fixes a Vulkan CTS test that would hang otherwise. Differential Revision: https://reviews.llvm.org/D105709
This commit is contained in:
Mirko Brkusanin
parent
d81a843846
commit
971f4173f8
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@ -2465,6 +2465,27 @@ bool AMDGPUInstructionSelector::selectG_AMDGPU_ATOMIC_CMPXCHG(
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return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
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}
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static bool isVCmpResult(Register Reg, MachineRegisterInfo &MRI) {
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if (Reg.isPhysical())
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return false;
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MachineInstr &MI = *MRI.getUniqueVRegDef(Reg);
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const unsigned Opcode = MI.getOpcode();
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if (Opcode == AMDGPU::COPY)
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return isVCmpResult(MI.getOperand(1).getReg(), MRI);
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if (Opcode == AMDGPU::G_AND || Opcode == AMDGPU::G_OR ||
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Opcode == AMDGPU::G_XOR)
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return isVCmpResult(MI.getOperand(1).getReg(), MRI) &&
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isVCmpResult(MI.getOperand(2).getReg(), MRI);
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if (Opcode == TargetOpcode::G_INTRINSIC)
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return MI.getIntrinsicID() == Intrinsic::amdgcn_class;
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return Opcode == AMDGPU::G_ICMP || Opcode == AMDGPU::G_FCMP;
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}
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bool AMDGPUInstructionSelector::selectG_BRCOND(MachineInstr &I) const {
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MachineBasicBlock *BB = I.getParent();
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MachineOperand &CondOp = I.getOperand(0);
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@ -2488,11 +2509,22 @@ bool AMDGPUInstructionSelector::selectG_BRCOND(MachineInstr &I) const {
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BrOpcode = AMDGPU::S_CBRANCH_SCC1;
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ConstrainRC = &AMDGPU::SReg_32RegClass;
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} else {
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// FIXME: Do we have to insert an and with exec here, like in SelectionDAG?
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// We sort of know that a VCC producer based on the register bank, that ands
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// inactive lanes with 0. What if there was a logical operation with vcc
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// producers in different blocks/with different exec masks?
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// FIXME: Should scc->vcc copies and with exec?
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// Unless the value of CondReg is a result of a V_CMP* instruction then we
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// need to insert an and with exec.
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if (!isVCmpResult(CondReg, *MRI)) {
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const bool Is64 = STI.isWave64();
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const unsigned Opcode = Is64 ? AMDGPU::S_AND_B64 : AMDGPU::S_AND_B32;
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const Register Exec = Is64 ? AMDGPU::EXEC : AMDGPU::EXEC_LO;
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Register TmpReg = MRI->createVirtualRegister(TRI.getBoolRC());
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BuildMI(*BB, &I, DL, TII.get(Opcode), TmpReg)
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.addReg(CondReg)
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.addReg(Exec);
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CondReg = TmpReg;
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}
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CondPhysReg = TRI.getVCC();
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BrOpcode = AMDGPU::S_CBRANCH_VCCNZ;
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ConstrainRC = TRI.getBoolRC();
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@ -174,3 +174,138 @@ body: |
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bb.1:
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...
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---
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name: brcond_class_intrinsic
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legalized: true
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regBankSelected: true
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body: |
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; GCN-LABEL: name: brcond_class_intrinsic
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x80000000)
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GCN: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; GCN: $vcc = COPY [[V_CMP_CLASS_F32_e64_]]
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; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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; GCN: bb.1:
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bb.0:
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liveins: $vgpr0, $vgpr1
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0:vgpr(s32), %1:vgpr(s32)
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G_BRCOND %2(s1), %bb.1
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bb.1:
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...
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---
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name: brcond_cmp_logic
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legalized: true
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regBankSelected: true
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body: |
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; GCN-LABEL: name: brcond_cmp_logic
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x80000000)
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
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; GCN: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
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; GCN: %5:sreg_64 = nofpexcept V_CMP_EQ_F32_e64 0, [[COPY2]], 0, [[COPY3]], 0, implicit $mode, implicit $exec
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; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_EQ_U32_e64_]], %5, implicit-def dead $scc
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; GCN: $vcc = COPY [[S_AND_B64_]]
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; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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; GCN: bb.1:
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = COPY $vgpr2
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%3:vgpr(s32) = COPY $vgpr3
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%4:vcc(s1) = G_ICMP intpred(eq), %0, %1
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%5:vcc(s1) = G_FCMP floatpred(oeq), %2, %3
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%6:vcc(s1) = G_AND %4, %5
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G_BRCOND %6(s1), %bb.1
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bb.1:
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...
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---
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name: brcond_logic
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legalized: true
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regBankSelected: true
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body: |
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; GCN-LABEL: name: brcond_logic
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x80000000)
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[COPY2]], implicit-def $scc
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; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
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; GCN: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
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; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc
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; GCN: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[S_AND_B64_]], $exec, implicit-def $scc
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; GCN: $vcc = COPY [[S_AND_B64_1]]
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; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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; GCN: bb.1:
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bb.0:
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liveins: $sgpr0, $vgpr0, $vgpr1
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:sgpr(s32) = COPY $sgpr0
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%3:sgpr(s1) = G_TRUNC %2(s32)
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%4:vcc(s1) = COPY %3(s1)
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%5:vcc(s1) = G_ICMP intpred(eq), %0, %1
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%6:vcc(s1) = G_AND %5, %4
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G_BRCOND %6(s1), %bb.1
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bb.1:
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...
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---
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name: brcond_logic_const
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legalized: true
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regBankSelected: true
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body: |
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; GCN-LABEL: name: brcond_logic_const
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x80000000)
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GCN: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
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; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 -1
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; GCN: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[V_CMP_EQ_U32_e64_]], [[S_MOV_B64_]], implicit-def dead $scc
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; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[S_XOR_B64_]], $exec, implicit-def $scc
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; GCN: $vcc = COPY [[S_AND_B64_]]
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; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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; GCN: bb.1:
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bb.0:
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liveins: $vgpr0, $vgpr1
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vcc(s1) = G_ICMP intpred(eq), %0, %1
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%3:sgpr(s1) = G_CONSTANT i1 true
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%4:vcc(s1) = COPY %3(s1)
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%5:vcc(s1) = G_XOR %2, %4
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G_BRCOND %5(s1), %bb.1
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bb.1:
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...
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