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[AMDGPU] Mark the scheduling model as complete

This commit is contained in:
Jay Foad 2020-02-28 13:22:44 +00:00
parent addcbc401c
commit 970558df94
1 changed files with 1 additions and 1 deletions
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2
llvm/lib/Target/AMDGPU/SISchedule.td
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@ -56,7 +56,7 @@ def Write16PassMAI : SchedWrite;
// instructions)
class SISchedMachineModel : SchedMachineModel {
let CompleteModel = 0;
let CompleteModel = 1;
// MicroOpBufferSize = 1 means that instructions will always be added
// the ready queue when they become available. This exposes them
// to the register pressure analysis.